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A426316B Dataheets PDF



Part Number A426316B
Manufacturers AMIC Technology
Logo AMIC Technology
Description 64K X 16 CMOS DYNAMIC RAM
Datasheet A426316B DatasheetA426316B Datasheet (PDF)

A426316B Series Preliminary Document Title 64K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE Revision History Rev. No. 0.0 64K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE History Initial issue Issue Date November 15, 2000 Remark Preliminary PRELIMINARY (November, 2000, Version 0.0) AMIC Technology, Inc. A426316B Series Preliminary Features n Organization: 65,536 words X 16 bits n Part Identification: - A426316B - A426316B-L (with self-refresh mode) n High speed - 30/35/40 ns RAS access time - 16.

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Document
A426316B Series Preliminary Document Title 64K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE Revision History Rev. No. 0.0 64K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE History Initial issue Issue Date November 15, 2000 Remark Preliminary PRELIMINARY (November, 2000, Version 0.0) AMIC Technology, Inc. A426316B Series Preliminary Features n Organization: 65,536 words X 16 bits n Part Identification: - A426316B - A426316B-L (with self-refresh mode) n High speed - 30/35/40 ns RAS access time - 16/18/20 ns column address access time - 10/11/12 ns CAS access time n Low power consumption - Operating: 75mA (-30 max) - Standby: 3 mA (TTL) Separate CAS ( UCAS , LCAS ) for byte selection Self refresh mode 256 refresh cycles, 4 ms refresh interval Read-modify-write, RAS -only, CAS -before- RAS , Hidden refresh capability n TTL-compatible, three-state I/O n JEDEC standard packages - 400mil, 40-pin SOJ - 400mil, 40/44 TSOP type II package n Single 5V power supply/built-in VBB generator n n n n 64K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE Pin Configuration n SOJ n TSOP Pin Descriptions Symbol VCC I/O0 I/O 1 I/O 2 I/O 3 VCC I/O 4 I/O 5 I/O 6 I/O 7 NC NC WE RAS NC A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS I/O 15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE NC A7 A6 A5 A4 VSS VCC I/O0 I/O 1 I/O 2 I/O 3 VCC I/O 4 I/O5 I/O 6 I/O 7 NC NC WE RAS NC A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 32 31 30 29 28 27 26 25 24 23 VSS I/O 15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE NC A7 A6 A5 A4 VSS Description Address Inputs Data Input/Output Row Address Strobe Column Address Strobe/Upper Byte Control Column Address Strobe/Lower Byte Control Write Enable Output Enable +5V Power Supply Ground No Connection A0 – A7 I/O0 - I/O15 RAS PRELIMINARY A426316BS (November, 2000, Version 0.0) A426316BV UCAS LCAS WE OE VCC VSS NC 1 AMIC Technology, Inc. A426316B Series Selection Guide Symbol tRAC tAA tCAC tOEA tRC tPC ICC1 ICC6 Description Maximum RAS Access Time Maximum Column Address Access Time Maximum CAS Access Time Maximum Output Enable ( OE ) Access Time Minimum Read or Write Cycle Time Minimum EDO Page Mode Cycle Time Maximum Operating Current Maximum CMOS Standby Current -30 30 16 10 10 65 12 95 2 -35 35 18 11 11 70 14 85 2 -40 40 20 12 12 75 15 75 2 Unit ns ns ns ns ns ns mA mA Functional Description The A426316B is a high performance CMOS Dynamic Random Access Memory organized as 65,536 words X 16 bits. The A426316B is fabricated with advanced CMOS technology and designed with innovative design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels. The A426316B features a high speed page mode operation in which high speed read, write and read-write are performed on any of the bits defined by the column address. The asynchronous column address uses an extremely short row address capture time to ease the system level timing constraints associated with multiplexed addressing. Output is tri-stated by a column address strobe ( UCAS and LCAS ) which acts as an output enable independent of RAS . Very EDO UCAS and LCAS to output access time eases system design. All inputs are TTL compatible. EDO Page Mode operation allows random access up to 256 X 16 bits within a page, with cycle time as short as 12/14/15 ns. The A426316B is best suited for graphics, digital signal processing and high performance peripherals. The A426316B is available in JEDEC standard 40-pin plastic SOJ package and 40/44 TSOP type II package. PRELIMINARY (November, 2000, Version 0.0) 2 AMIC Technology, Inc. A426316B Series Block Diagram I/O15 I/O14 I/O13 I/O12 I/O 11 I/O 10 I/O9 I/O8 VCC VSS REFRESH CONTROLLER Y0 - Y7 COLUMN DECODER SENSE AMP UPPER BYTE DATA I/O BUFFER 256 X 16 LOWER BYTE DATA I/O BUFFER A0 RAS RAS CLOCK GENERATOR A1 A2 A3 A4 A5 UCAS UCAS CLOCK GENERATOR A6 A7 ADDRESS BUFFERS ROW DECODER 256 256 X 256 X 16 ARRAY X0 - X7 I/O7 I/O6 I/O5 I/O4 I/O 3 I/O 2 I/O 1 I/O 0 LCAS LCAS CLOCK GENERATOR WE WE CLOCK GENERATOR OE OE CLOCK GENERATOR SUBSTRATE BIAS GENERATOR Recommended Operating Conditions Symbol VCC VSS VIH VIL Input Voltage Description Supply Voltage (Ta = 0°C to +70°C) Min. 4.5 0.0 2.4 -1.0 Typ. 5.0 0.0 Max. 5.5 0.0 VCC + 1 0.8 Unit V V V V PRELIMINARY (November, 2000, Version 0.0) 3 AMIC Technology, Inc. A426316B Series Truth Table Function Standby Read: Word Read: Lower Byte RAS UCAS H L H LCAS H L L WE OE Address X Row/Col. Row/Col. I/Os High-Z Data Out I/O0-7 = Data Out I/O8-15 = High-Z I/O0-7 = High-Z I/O8-15 = Data Out Data In I/O0-7 = Data In I/O8-15 = X I/O0-7 = X I/O8-15 = Data In Data Out → Data In Data Out Data Out Data In Data In Data In Data In Data Out Data In → High-Z High-Z High-Z High-Z Notes H L L X H H X L L Read: Upper Byte L L H H L Row/Col. Wri.


A4255CLN A426316B A428316


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