Phase-locked-loop. 74HCT7046A Datasheet


74HCT7046A Phase-locked-loop. Datasheet pdf. Equivalent


Part Number

74HCT7046A

Description

Phase-locked-loop

Manufacture

NXP

Total Page 30 Pages
Datasheet
Download 74HCT7046A Datasheet


74HCT7046A
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT7046A
Phase-locked-loop with lock
detector
Product specification
File under Integrated Circuits, IC06
December 1990

74HCT7046A
Philips Semiconductors
Phase-locked-loop with lock detector
Product specification
74HC/HCT7046A
FEATURES
Low power consumption
Centre frequency up to 17 MHz
(typ.) at VCC = 4.5 V
Choice of two phase comparators:
EXCLUSIVE-OR;
edge-triggered JK flip-flop;
Excellent VCO frequency linearity
VCO-inhibit control for ON/OFF
keying and for low standby power
consumption
Minimal frequency drift
Operation power supply voltage
range:
VCO section 3.0 to 6.0 V
digital section 2.0 to 6.0 V
Zero voltage offset due to op-amp
buffering
Output capability: standard
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT7046 are high-speed
Si-gate CMOS devices and are
specified in compliance with JEDEC
standard no. 7.
The 74HC/HCT7046 are
phase-locked-loop circuits that
comprise a linear voltage-controlled
oscillator (VCO) and two different
phase comparators (PC1 and PC2)
with a common signal input amplifier
and a common comparator input.
A lock detector is provided and this
gives a HIGH level at pin 1 (LD) when
the PLL is locked. The lock detector
capacitor must be connected
between pin 15 (CLD) and pin 8
(GND). The value of the CLD capacitor
can be determined, using information
supplied in Fig.32. The input signal
can be directly coupled to large
voltage signals, or indirectly coupled
(with a series capacitor) to small
voltage signals. A self-bias input
circuit keeps small voltage signals
within the linear region of the input
amplifiers. With a passive low-pass
filter, the “7046” forms a second-order
loop PLL. The excellent VCO linearity
is achieved by the use of linear
op-amp techniques.
VCO
The VCO requires one external
capacitor C1 (between C1A and C1B)
and one external resistor R1
(between R1 and GND) or two
external resistors R1 and R2
(between R1 and GND, and R2 and
GND). Resistor R1 and capacitor C1
determine the frequency range of the
VCO. Resistor R2 enables the VCO
to have a frequency offset if required.
The high input impedance of the VCO
simplifies the design of low-pass
filters by giving the designer a wide
choice of resistor/capacitor ranges. In
order not to load the low-pass filter, a
demodulator output of the VCO input
voltage is provided at pin 10
(DEMOUT). In contrast to conventional
techniques where the DEMOUT
voltage is one threshold voltage lower
than the VCO input voltage, here the
DEMOUT voltage equals that of the
VCO input. If DEMOUT is used, a load
resistor (RS) should be connected
from DEMOUT to GND; if unused,
DEMOUT should be left open. The
VCO output (VCOOUT) can be
connected directly to the comparator
input (COMPIN), or connected via a
frequency-divider. The VCO output
signal has a duty factor of 50%
(maximum expected deviation 1%), if
the VCO input is held at a constant
DC level. A LOW level at the inhibit
input (INH) enables the VCO and
demodulator, while a HIGH level turns
both off to minimize standby power
consumption.
The only difference between the HC
and HCT versions is the input level
specification of the INH input. This
input disables the VCO section. The
comparators’ sections are identical,
so that there is no difference in the
SIGIN (pin 14) or COMPIN (pin 3)
inputs between the HC and HCT
versions.
Phase comparators
The signal input (SIGIN) can be
directly coupled to the self-biasing
amplifier at pin 14, provided that the
signal swing is between the standard
HC family input logic levels.
Capacitive coupling is required for
signals with smaller swings.
Phase comparator 1 (PC1)
This is an EXCLUSIVE-OR network.
The signal and comparator input
frequencies (fi) must have a 50% duty
factor to obtain the maximum locking
range. The transfer characteristic of
PC1, assuming ripple (fr = 2fi) is
suppressed,
is:
VDEMOUT = -V---π-C---C-- ( φSIGIN φCOMPIN)
where VDEMOUT is the demodulator
output at pin 10;
VDEMOUT = VPC1OUT (via low-pass
filter).
The phase comparator gain
is:
Kp = -V---π-C---C-- (V r) .
The average output voltage from
PC1, fed to the VCO input via the
low-pass filter and seen at the
demodulator output at pin 10
(VDEMOUT), is the resultant of the
phase differences of signals (SIGIN)
and the comparator input (COMPIN)
as shown in Fig.6. The average of
VDEMOUT is equal to 1/2 VCC when
there is no signal or noise at SIGIN
and with this input the VCO oscillates
at the centre frequency (fo). Typical
December 1990
2


Features INTEGRATED CIRCUITS DATA SHEET For a co mplete data sheet, please also download : • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74H C/HCT/HCU/HCMOS Logic Package Informati on • The IC06 74HC/HCT/HCU/HCMOS Logi c Package Outlines 74HC/HCT7046A Phase -locked-loop with lock detector Product specification File under Integrated C ircuits, IC06 December 1990 Philips Se miconductors Product specification P hase-locked-loop with lock detector FEA TURES • Low power consumption • Cen tre frequency up to 17 MHz (typ.) at VC C = 4.5 V • Choice of two phase compa rators: EXCLUSIVE-OR; edge-triggered JK flip-flop; • Excellent VCO frequency linearity • VCO-inhibit control for ON/OFF keying and for low standby power consumption • Minimal frequency drif t • Operation power supply voltage ra nge: VCO section 3.0 to 6.0 V digital s ection 2.0 to 6.0 V • Zero voltage of fset due to op-amp buffering • Output capability: standard • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT7046 are high-spe.
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