Document
CT1820 Data Terminal Bit Processor for MIL-STD-1553 A & B
Features
• Performs Encoder, Decoder, Logic and Control functions of a Data Bus Terminal to MIL-STD-1553 specifications, including Address, Mode Code and Broadcast Decoding and Terminal Fail Safe • Flexibility - all control lines accessible • Parallel tri-state subsystem l/O bus compatible with both 16 bit and 8 bit systems • Dual rank l/O registers for versatile subsystem tlmlng X LA LE • Operates from +5VDC @ 40mA typical (25mA CT1820) F • Self-contained oscillator and clock driver • Look-ahead serial receive data output • Self-test, on-line wraparound, plus off-line capability 9001
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A E RO
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ISO
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1
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General Description
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RTIFIED
The CT1555-3/CT1820 Bit Processor Unit (BPU) is an advanced Hybrid Microcircuit that provides the interface between a MIL-STD-1553 Transceiver such as CT3231M or CT3232M, and the subsystem internal parallel data bus. The unit can be employed as the mux bus interface for Remote Subsystems or Master Terminal Bus Controllers, thus providing a common interface for all systems communicating over the bus. The unit places no restrictions on Command, Response or polling operations as it transfers all Command, Status and Data words from the bus to parallel output lines, together with error information, bus status and handshaking signals. It also contains 5 Bit Address Recognition, Broadcast and Mode Code Decode, Terminal Fail Safe Signal and Self Test. In the transmit mode, it accepts parallel data from the user and transmits Command, Status and Data words, under subsystem control, to the data bus. Positive handshaking signals provide logic control synchronisation between the unit and the subsystem for direct data flow. The hybrid is completely compatible with all the electrical and functional spec requirements of MIL-STD-1553 A & B.
43 DATA SELECT 2 45 46 47 48 50 44 41 42 54 56 56 53 43 43 43 LOAD DATA 2 LOAD DATA 1
DATA SELECT 1 7
2
3
4
5
6
(OPTIONAL) SERIAL INPUT
(MSB) D15
FIRST RANK REC’V REG DO - D7
SECOND RANK REC’V REG DO - D7
FIRST RANK XMT REG DO - D7
LATCH DATA 1
(LSB) D0
LATCH DATA 2
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
SECOND RANK XMT REG DO - D7
Vcc 1 +5V GND GND 11 34
FIRST RANK REC’V REG D8 - D15
SECOND RANK REC’V REG D8 - D15
FIRST RANK XMT REG D8 - D15
SECOND RANK XMT REG D8 - D15
CASE 20
36 32
SERIAL DATA OUT RT ENABLE (MSB) A4 BUILT IN TEST SELECT ADDRESS DECODE MANCHESTER DECODER & CONTROL LOGIC MANCHESTER ENCODER & CONTROL LOGIC DATA IN DATA IN 21 22
5 BIT ADDRESS
{
12 8 9 A1 10 13 (LSB) A0 A3 A2
BIT SELECT DATA OUT DATA OUT
19 25 26
39
BROADCAST
BROADCAST DECODE
FAIL SAFE TIMER & CONTROL
FAIL SAFE
15
SEND DATA ESCOUT SYNC SEL
27 28 24 23 35 38 30 29 18
40
MODE CODE
MODE CODE DECODE
ENC ENA OUTPUT INH MRST +5V OSC / CLOCK POWER OSC & CLOCK DRIVER XTAL CLOCK OUT
14 16 33 37 31
VALID WORD COMM/DATA SYNC DEC RST TAKE DATA DSC OUT
CLOCK IN
17
Figure 1 – Functional Diagram eroflex Circuit Technology – Data Bus Modules For The Future © SCDCT1820 REV D 6/25/99
RX DATA IN
32 25 33 1
TX DATA IN TX DATA IN
DATA OUT DATA OUT
25 DATA 26
TX DATA OUT DATA BUS TX DATA OUT
CT3231 T/R HYBRID
2 7 RX DATA OUT
CT1820 OR CT1553 BIT PROCESSOR
DATA IN 21 DATA IN 29 XTAL 12 MHz 22
16 BIT OR 8 BIT SUBSYSYEM
26 RX DATA IN 31
RX DATA 10 OUT
CONTROL
TX INHIBIT
Figure 2 – Typical MIL-STD-1553 Data Terminal Absolute Maximum Ratings
Parameter Supply Voltage Logic Input Voltage Logic Input Current Clock Output Current (Pin 18) Clock In (Pin 17) Storage Temperature Range Operating Case Temperature Range +7.0 -0.3 to +5.5 -20 to +4 15 -0.3 to VCC +0.3V -65 to +150 -55 to +125 Units V V mA mA V °C °C
Electrical Characteristics
(VCC = 5.0V ±5%) Sym VIH VIL VOH VOL VIHC VILC VOHC VOLC lOC lOSC Parameter / Conditions Logic "1" Input Voltage Logic "0" Input Voltage Logic "1" Output Voltage Logic "0" Output Voltage Logic "1" Input Voltage (CLOCK) Logic "0" Input Voltage (CLOCK) Logic "1" Output Voltage (CLOCK) Logic "0" Output Voltage (CLOCK) Logic Supply Current Oscillator / Clock Supply Current
2
Min 2.0 -
Typ -
Max 0.7
Units V V
See Pin assignments and Loading See Pin assignments and Loading VCC-0.5 VCC-0.3 40 8 GND+0.5 GND+0.3 13 V V V V mA mA
Aeroflex Circuit Technology
SCDCT1820 REV D 6/25/99 Plainview NY (516) 694-6700
PIN ASSIGNMENTS AND LOADING
In the following table, the symbols are defined as follows: IIH= maximum input HIGH current with V IN = 2.5 volts IIL = maximum input LOW current with VIN = 0.4 volts IOH = maximum output HIGH current for VOUT = 2.5 volts minimum IOL = maximum output LOW current for VOUT = 0.4 volts maximum * Indicates use of an internal pull-up resistor
Pin No Name I IH (µA) VCC D8 D9 D10 D11 D12 DATA SELECT 1 A3* A2* A1* GROUND A4* A0* VALID WORD FAIL SAFE COMM / DATA SYNC CLOCK IN CLOCK OUT S / T SELECT CASE DATA IN DATA IN 20 20 -0.4 -0.4 20 20 -0.4 -0.4 40 -0.8 ±30 ±0.003 -1000 1.0 20 -0.4 -400 -400 - 38.