Document
CT2565 Bus Controller, Remote Terminal and BUS Monitor
FOR MIL-STD-1553B
Features
I I I I I I I I I I I
Second Source Compatible to the BUS-65600 RTU implements all dual redundant mode codes Selective mode code illegalization available 16 bit microprocessor compatibility BC checks status word for correct address and set flags RTU illegal mode codes externally selectable 16 bit µProcessor compatibility DMA handshaking for subsystem message transfers MIL-PRF-38534 compliant circuits available DESC SMD #5962–88585 Pending Packaging – Hermetic Metal • 78 Pin, 2.1" x 1.87" x .25" Plug-In type package • 82 Lead, 2.2" x 1.61" x .18" Flat package
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General Description
The CT2565 is a dual redundant MIL-STD-1553 Bus Controller (BC), Remote Terminal (RT), and Bus Monitor, (BM) Bus packaged in a 1.9" x 2.1" hermetic hybrid. It provides all the functions required to interface a MIL-STD-1553 dual redundant serial data bus transceiver, (Aeroflex's ACT4487 for example) and a subsystem parallel three-state data bus. Utilizing a custom monolithic IC, the CT2565 provides selectable operation as a Bus Controller, Remote Terminal or a Bus Monitor (BM). The CT2565 is compatible with most µprocessors. It provides a 16 bit three-state parallel data bus and uses direct memory access (DMA type) handshaking for subsystem transfers. All message transfer timing as well as DMA and control lines are provided internally. Subsystem overhead associated with message transfers is therefore minimized. Interface control lines are common for both BC and RT operation. The CT2565 features the capability for implementing all dual redundant MIL-STD-1553 mode codes. In addition, any mode code may (optional) be illegalized through the use of an external (200ns access time) PROM. Complete error detection capability is provided, for both BC and RTU operation. Error detection includes: response time-out, inter message gaps, sync, parity, Manchester, word count and bit count. The CT2565 complies with all the requirements of MIL-STD-1553. The hybrid is screened in accordance with the requirements of MIL-STD-883 and operates over the full military temperature range of -55°C to +125°C. eroflex Circuit Technology – Data Bus Modules For The Future © SCDCT2565 REV B 8/10/99
STATUS INPUTS
Aeroflex Circuit Technology
RTADDR
DBACCEPT SSFLAG SERREQ SSERR SSBUSY
MODE CODE CONTROL CH A CONTROL REMOTE TERMINAL LOGIC
TXINH A TXDATA A TXDATA A RXDATA A RXDATA A
CH A ENCODE/ DECODE
WC0-WC4 T/R LMC ILLCMD
I/O0 - I/O16 DATA BUFFERS
DATA BUS
BUFENA
R/W
EN
2 CH B CONTROL CONTROL BUS BUS CONTROLLER LOGIC I/O BUS I/O LOGIC BUFFERS PARITY CHECKER
TXINH TXDATA TXDATA RXDATA RXDATA
B B B B B
CH B ENCODE/ DECODE
RTADDR
RTADR0 RTADR1 RTADR2 RTADR3 RTADR4 RTADRP
RTADDR
BUSREQ BUSGRNT BUSACK TIMEOUT SOM EOM INCMD CS OE WR TESTIN TESTOUT RT/BC MT BCSTART CHA/CHB LOOPERR MSGERR STATERR LWORD HSFAIL STATEN BITEN NBGRNT ADRINC NODT BSCTRCV
12MHz
SCDCT2565 REV B 8/10/99 Plainview NY (516) 694-6700
Figure 1 – CT2565 Block Diagram
Values at nominal Power Supply Voltages unless otherwise specified PARAMETER Logic VIH VIL VOH VOL IIH IIL IOL * IOH * CIN (f = 1MHz) COUT (f = 1MHz) Power Supply +5VDC Tolerances Supply Current Internal Decoupling Temperature Range Operating (Case) Storage Physical Characteristics Size 78 pin DDIP 82 pin flatpack Weight VALUE 2.0 min 0.8 max 3.7 min 0.4 max ±100 max -0.4 max ±1.2 max ±0.4 max 20 max 20 max UNITS V V V V µA mA mA mA pF pF
±10 max 50 typ (70 max) 1.5 typ
−55 to +125 −65 to +150
% mA µF °C °C
1.9 x 2.10 x 0.25 (48.30 x 53.34 x 6.35) 1.6 x 2.19 x 0.15 (40.64 x 55.63 x 3.81) 1.7 (48)
in (mm) in (mm) oz (g)
* I OL and IOH parameters are indicated for all logic outputs except Data Bus (DB0 – DB15) which are ±5mA for both parameters.
Table 1 – CT2565 Specifications
GENERAL The CT2565 uses a custom CMOS ASIC for protocol logic and I/O buffering to provide low power dissipation in its small package. The CT2565 performs a continuous on-line Built-In-Test (BIT); in this test the last transmitted word of each message transfer is wrapped around through the active receiver channel and verified against the captured encoded word. A user-defined loop test under subsystem control can also be implemented. Numerous error flags are provided to the subsystem including message error, status error, response time out and loop test error. An external 12 MHz, TTL clock connected to Pin 39 is required. Where appropriate, references to signal names and their associated pin numbers for the 78 pin
Aeroflex Circuit Technology
DDIP package are made throughout this document. For flatpack model pin numbers, refer to Table 10. BC/RTU/MT Initialization The CT2565 provides BC, RTU, and MT operating modes. The operating mode if dynamically selectable through two static control inputs as listed in Table 2. It is recommended that a master RESET signal be issued .