Document
CT2566 MIL-STD-1553 to Microprocessor Interface Unit
Features
• • • • • • • • • • Second Source Compatible to the BUS-66300 PGA Version available, (second source to the BUS-66312) Compatible with MIL-STD-1750 CPUs Compatible with MOTOROLA, INTEL, and ZILOG CPUs Compatible with Aeroflex’s CT2565 BC/RT/MT and CT2512 RT Minimizes CPU overhead Signal controls for shared memory implementation Transfers complete messages to shared memory Provides memory mapped 1553 interface Packaging – Hermetic Metal
• 78 Pin, 2.1" x 1.87" x .25" PGA type package • 82 Lead, 2.2" x 1.61 x .18" Flat Package
CIRCUIT TECHNOLOGY
www.aeroflex.com
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Description
Aeroflex CT2566 MIL-STD-1553 to Microprocessor Interface Unit simplifies the CPU to 1553 Data Bus interface. The CT2566 provides an interface by using RAM allowing the CPU to transmit or receive 1553 traffic simply by accessing the memory. All 1553 message transfers are entirely memory or I/O mapped. The CT2566 supports 1553 interface devices such as Aeroflex's CT2512 dual RT or the CT2565 dual BC, RT, and MT. The CT2566 operates over the full military -55°C to +125°C temperature range.
CLOCK IN
MSTRCLR SELECT STRBD READYD RD/WR MEM/REG EXTEN EXTLD
CPU TIMING
MEMORY TIMING
IOEN BUSREQ BUSGRNT BUSACK CS OE WR MEMCS MEMOE MEMWR ADRINC NBGRNT BCSTART TAGEN EOM SOM BLOCK STATUS WORD MSGERR TIMEOUT STATERR LOOPERR CHB/CHA CTLINB/A CTLOUT B/A RTU/BC MT DBAC SSBUSY SSFLAG SVCREQ RESET
CONTENTION RESOLVER
MICROCODE CONTROLLER
A15-A00 D15-D00
OPERATION CONTROL REGISTERS CONFIGURATION REGISTER START / RESET REGISTER INTERRUPT MASK REGISTER INT INTERRUPT GENERATOR
Figure 1 – Functional Block Diagram eroflex Circuit Technology – Data Bus Modules For The Future © SCDCT2566 REV B 8/10/99
PARAMETER
Specifications at Nominal Power Supply Voltages VALUE
−630 −700
UNITS
Logic IIH (With VIH = 2.7V) IIL (With VIL = 0.0V) IOH IOL VIH VIL VOH VOL Clock Power Supplies Voltage Current Drain Temperature Range Operating (Case) Storage Physical Characteristics Size 78 pin DIP 82 pin flatpack Weight 78 pin DIP 82 pin flatpack
µA µA mA mA V V V V MHz V mA °C °C
4.0 min 4.0 2.0 0.8 3.7 0.4 12 5.0±10% 10 typ
−55 to +125 −65 to +150
2.1 x 1.87 x 0.25 (53 x 47.5 x 6.4) 2.1 x 1.87 x 0.25 (55.6 x 40.6 x 3.71) 1 (28) 1 (28)
in (mm) in (mm) oz (g) oz (g)
Table 1 – Specifications
GENERAL The CT2566 was designed to perform required handshaking to the 1553 interface device, storing or retrieving message(s) from a user supplied RAM and notifying the CPU that a 1553 transaction has occurred. The CPU uses this RAM to read the received data as well as to store messages to be transmitted onto the Bus. The CT2566 can be used to implement BC, RT, or MT operation and can be either memory mapped or I/O mapped to CPU address space. Registers internal to the CT2566 control its operation. The CT2566 can access up to four external, user supplied registers and can address up to 64K words of RAM. The RAM selected must be a non-latched static RAM (capable of meeting the timing constraints for the CT2566). A double
Aeroflex Circuit Technology
buffering architecture is provided to prevent incomplete or partially updated information from being transmitted onto the 1553 Data Bus. The CT2566 requires an external, user supplied clock. COMPATIBLE MICROPROCESSOR TYPES The CT2566 may be used with most common microprocessors, including, the Motorola 68000 family, the Intel 8080 family, Zilog Z8000 products, and available MIL-STD-1750 processors. Interfacing the CT2566 to the 1553 Data Bus requires external circuitry such as Aeroflex’s CT2565(BC/RT/MT) and ACT4489D transceivers. Figure 2 shows the interconnection for these components.
2
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14
NAME SELECT RD/WR READYD EXTEN TAGEN EOM SOM STATERR ADRINC MEM/REG CLOCK IN LOOPERR BUSREQ BUSGRNT
I/O I I O O O I I I I I I I I O
DESCRIPTION Select. When active, selects CT2566 for operation. Read/Write. Controls CPU bus data direction. Ready Data. When active indicates data has been received from, or is available to the CPU. External Enable. Output from CT2566 to enable output from external devices. Same timing as MEMOE. Tag Enable. Enables an external time tag counter for transferring the time tag word into memory. End of Message. Input from 1553 device indicating end of message. Start of Message. Input from 1553 device indicating start of message in RTU mode. Status Error. Input from 1553 device when status word has either a bit set or unexpected RT address (in BC mode only). Address Increment. Sent from 1553 device to increment address counter following word transfer. Memory/Register. Input from CPU to select memory or register data transfer. Clock input; 50% duty cycle, 12MHz, max. Loop Error. Input from 1553 device if short loop BIT fails. Bus Request. When active, indicates 1553 device requires use of the address/data bus. Bus Gra.