Document
Features
• EE Programmable 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-, 2,097,152 x 1-, and • • • • • • • •
4,194,304 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays (FPGAs) Available as a 3.3V (±10%) Commercial and Industrial Version Simple Interface to SRAM FPGAs Pin Compatible with Xilinx® XC17SXXXA and XC17SXXXXL PROMs Compatible with Xilinx Spartan®-II, Spartan-IIE and Spartan XL FPGAs in Master Serial Mode Very Low-power CMOS EEPROM Process Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC Packages), 8-lead PDIP, 8-lead SOIC, 20-lead SOIC and 44-lead TQFP Packages for a Specific Density Low-power Standby Mode High-reliability – Endurance: Minimum 10 Write Cycles – Data Retention: 20 Years at 85°C
FPGA Configuration Memory AT17N256 AT17N512 AT17N010 AT17N002 AT17N040 3.3V System Support
Description
The AT17N series FPGA Configuration EEPROM (Configurators) provide an easy-touse, cost-effective configuration memory for Field Programmable Gate Arrays. The AT17N series device is packaged in the 8-lead LAP, 8-lead PDIP, 8-lead SOIC, 20-lead SOIC and 44-lead TQFP, see Table 1. The AT17N series Configurators uses a simple serial-access procedure to configure one or more FPGA devices. The AT17N series configurators can be programmed with industry-standard programmers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable and factory programming. Table 1. AT17N Series Packages
Package 8-lead LAP 8-lead PDIP 8-lead SOIC 20-lead SOIC 44-lead TQFP Note: AT17N256 – Yes Yes Yes – AT17N512/ AT17N010 Yes Yes Use 8-lead LAP Yes –
(1)
AT17N002 Yes – Use 8-lead LAP Yes Yes
(1)
AT17N040 – – – – Yes
1. The 8-lead LAP package has the same footprint as the 8-lead SOIC. Since an 8lead SOIC package is not available for the AT17N512/010/002 devices, it is possible to use an 8-lead LAP package instead.
Rev. 3020A–CNFG–05/03
1
Pin Configuration
8-lead LAP
DATA CLK RESET/OE CE
1 2 3 4
8 7 6 5
VCC VCC (SER_EN) DC GND
8-lead SOIC
DATA CLK RESET/OE CE
1 2 3 4
8 7 6 5
VCC VCC (SER_EN) DC GND
8-lead PDIP
DATA CLK RESET/OE CE
1 2 3 4
8 7 6 5
VCC VCC (SER_EN) DC GND
20-lead SOIC
DATA NC CLK NC NC NC NC RESET/OE NC CE
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC NC VCC (SER_EN) NC NC NC NC DC NC GND
2
AT17N256/512/010/002/040
3020A–CNFG–04/10/03
AT17N256/512/010/002/040
44 TQFP
NC CLK NC NC DATA NC VCC NC NC VCC (SER_EN) NC 44 43 42 41 40 39 38 37 36 35 34
NC NC NC NC NC NC DC NC NC NC NC
1 2 3 4 5 6 7 8 9 10 11
12 13 14 15 16 17 18 19 20 21 22
33 32 31 30 29 28 27 26 25 24 23
NC NC NC NC NC NC NC NC NC NC DC
NC RESET/OE NC CE NC NC GND NC NC DC NC
3
3020A–CNFG–04/10/03
Block Diagram
SER_EN
POWER ON RESET
Device Description
The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) interface directly with the FPGA device control signals. All FPGA devices can control the entire configuration process and retrieve data from th.