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ARM7TDMI Dataheets PDF



Part Number ARM7TDMI
Manufacturers ETC
Logo ETC
Description general purpose 32-bit microprocessors
Datasheet ARM7TDMI DatasheetARM7TDMI Datasheet (PDF)

ARM 7TDMI Data Sheet Document Number:ARM DDI 0029E Copyright Advanced RISC Machines Ltd (ARM) 1995 All rights reserved Proprietary Notice ARM, the ARM Powered logo, EmbeddedICE, BlackICE and ICEbreaker are trademarks of Advanced RISC Machines Ltd. Neither the whole nor any part of the information contained in, or the product described in, this datasheet may be adapted or reproduced in any material form except with the prior written permission of the copyright holder. The product described in t.

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ARM 7TDMI Data Sheet Document Number:ARM DDI 0029E Copyright Advanced RISC Machines Ltd (ARM) 1995 All rights reserved Proprietary Notice ARM, the ARM Powered logo, EmbeddedICE, BlackICE and ICEbreaker are trademarks of Advanced RISC Machines Ltd. Neither the whole nor any part of the information contained in, or the product described in, this datasheet may be adapted or reproduced in any material form except with the prior written permission of the copyright holder. The product described in this datasheet is subject to continuous developments and improvements. All particulars of the product and its use contained in this datasheet are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties or merchantability, or fitness for purpose, are excluded. This datasheet is intended only to assist the reader in the use of the product. ARM Ltd shall not be liable for any loss or damage arising from the use of any information in this datasheet, or any error or omission in such information, or any incorrect use of the product. Change Log Issue A (Draft 0.1) (Draft 0.2) B C D draft1 D E Date Sept 1994 Oct 1994 Dec 1994 Dec 1994 Mar 1995 Mar 1995 Mar 1995 Aug 1995 By EH/BJH EH EH/AW AW AW AW AW AP Change Created. First pass review comments added. First formal release Further review comments Reissued with open access status. No change to the content. Changes in line with the ARM7TDM datasheet. Further technical changes. Review comments added. Signals added plus minor changes. ARM Advanced RISC Machines Open Access Issued: August 1995 Key: Open Access No confidentiality To enable document tracking, the document number has two codes: Major release A B etc Draft Status draft1 draft2 etc E Full and complete First Draft Second Draft etc Embargoed (date given) Pre-release First release Second release etc Open Access ii ARM7TDMI Data Sheet ARM DDI 0029E 1 11 TOC 1 Introduction 1.1 1.2 1.3 1.4 1.5 Introduction ARM7TDMI Architecture ARM7TDMI Block Diagram ARM7TDMI Core Diagram ARM7TDMI Functional Diagram Contents 1-2 1-2 1-4 1-5 1-6 2 Signal Description 2.1 Signal Description 2-1 2-2 3 Programmer’s Model 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 Processor Operating States Switching State Memory Formats Instruction Length Data Types Operating Modes Registers The Program Status Registers Exceptions Interrupt Latencies Reset 3-1 3-2 3-2 3-2 3-3 3-3 3-4 3-4 3-8 3-10 3-14 3-15 ARM7TDMI Data Sheet ARM DDI 0029E Contents-i Open Access 1-1 Contents 4 ARM Instruction Set 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 4.16 4.17 4.18 Instruction Set Summary The Condition Field Branch and Exchange (BX) Branch and Branch with Link (B, BL) Data Processing PSR Transfer (MRS, MSR) Multiply and Multiply-Accumulate (MUL, MLA) Multiply Long and Multiply-Accumulate Long (MULL,MLAL) Single Data Transfer (LDR, STR) Halfword and Signed Data Transfer Block Data Transfer (LDM, STM) Single Data Swap (SWP) Software Interrupt (SWI) Coprocessor Data Operations (CDP) Coprocessor Data Transfers (LDC, STC) Coprocessor Register Transfers (MRC, MCR) Undefined Instruction Instruction Set Examples 4-1 4-2 4-5 4-6 4-8 4-10 4-18 4-23 4-25 4-28 4-34 4-40 4-47 4-49 4-51 4-53 4-57 4-60 4-61 Open Access 5 THUMB Instruction Set 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 Format 1: move shifted register Format 2: add/subtract Format 3: move/compare/add/subtract immediate Format 4: ALU operations Format 5: Hi register operations/branch exchange Format 6: PC-relative load Format 7: load/store with register offset Format 8: load/store sign-extended byte/halfword Format 9: load/store with immediate offset Format 10: load/store halfword Format 11: SP-relative load/store Format 12: load address Format 13: add offset to Stack Pointer Format 14: push/pop registers Format 15: multiple load/store Format 16: conditional branch Format 17: software interrupt 5-1 5-5 5-7 5-9 5-11 5-13 5-16 5-18 5-20 5-22 5-24 5-26 5-28 5-30 5-32 5-34 5-36 5-38 Contents-ii ARM7TDMI Data Sheet ARM DDI 0029E Contents 5.18 5.19 5.20 Format 18: unconditional branch Format 19: long branch with link Instruction Set Examples 5-39 5-40 5-42 6 Memory Interface 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 Overview Cycle Types Address Timing Data Transfer Size Instruction Fetch Memory Management Locked Operations Stretching Access Times The ARM Data Bus The External Data Bus 6-1 6-2 6-2 6-4 6-9 6-10 6-12 6-12 6-12 6-13 6-15 7 Coprocessor Interface 7.1 7.2 7.3 7.4 7.5 7.6 Overview Interface Signals Register Transfer Cycle Privileged Instructions Idempotency Undefined Instructions 7-1 8 Debug Interface 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 Overview Debug Systems Debug Interface Signals Scan Chains and JTAG Interface Reset Pullup Resistors Instruction Register Public Instructions Test Data Registers ARM7TDMI Core Clocks Determining the Co.


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