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AS4LC4M16S0 Dataheets PDF



Part Number AS4LC4M16S0
Manufacturers ETC
Logo ETC
Description 3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM
Datasheet AS4LC4M16S0 DatasheetAS4LC4M16S0 Datasheet (PDF)

Advance information ® AS4LC8M8S0 AS4LC4M16S0 3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM Features • PC100/133 compliant • Organization - 2,097,152 words × 8 bits × 4 banks (8M×8) - 1,048,576 words × 16 bits × 4 banks (4M×16) • Fully synchronous - All signals referenced to positive edge of clock • Four internal banks controlled by BA0/BA1 (bank select) • High speed - 133/125/100 MHz - 5.4 ns (133 MHz)/6 ns (125/100 MHz) clock access time • Low power consumption - Standby: 7.2 mW max, CMOS I/O • .

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Advance information ® AS4LC8M8S0 AS4LC4M16S0 3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM Features • PC100/133 compliant • Organization - 2,097,152 words × 8 bits × 4 banks (8M×8) - 1,048,576 words × 16 bits × 4 banks (4M×16) • Fully synchronous - All signals referenced to positive edge of clock • Four internal banks controlled by BA0/BA1 (bank select) • High speed - 133/125/100 MHz - 5.4 ns (133 MHz)/6 ns (125/100 MHz) clock access time • Low power consumption - Standby: 7.2 mW max, CMOS I/O • 4096 refresh cycles, 64 ms refresh interval • Auto refresh and self refresh • Automatic and direct precharge • Burst read, single write operation • Can assert random column address in every cycle • LVTTL compatible I/O • 3.3V power supply • JEDEC standard package, pinout and function - 400 mil, 54-pin TSOP II • Read/write data masking • Programmable burst length (1/2/4/8/full page) • Programmable burst sequence (sequential/interleaved) • Programmable CAS latency (2/3) Pin arrangement AS4LC4M16S0 VCC DQ0 VCCQ NC DQ1 VSSQ NC DQ2 VCCQ NC DQ3 VSSQ NC VCC NC WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VCC VCC DQ0 VCCQ DQ1 DQ2 VSSQ DQ3 DQ4 VCCQ DQ5 DQ6 VSSQ DQ7 VCC LDQM WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ15 VSSQ DQ14 DQ13 VCCQ DQ12 DQ11 VSSQ DQ10 DQ9 VCCQ DQ8 VSS NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS VSS DQ7 VSSQ NC DQ6 VCCQ NC DQ5 VSSQ NC DQ4 VCCQ NC VSS NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS Pin designation Pin(s) DQM (8M×8) UDQM/LDQM (4M×16) A0 to A11 BA0, BA1 DQ0 to DQ7 (8M×8) DQ0 to DQ15 (4M×16) RAS CAS WE CS VCC, VCCQ VSS, VSSQ CLK CKE Description Output disable/write mask Address inputs Bank select inputs Input/output Row address strobe Column address strobe Write enable Chip select Power (3.3V ± 0.3V) Ground Clock input Clock enable AS4LC4M16S0 Selection guide Symbol Bus frequency Minimum clock access time Minimum setup time Minimum hold time Minimum RAS to CAS delay Minimum RAS precharge time Remarks: (CL/tRCD/tRP) CL = 2 CL = 3 fmax tAC tAC tS tH tRCD tRP -75 (PC133) 133 – 5.4 1.5 0.8 3 3 3/3/3 -8 125 – 6 2 1.0 3 3 3/3/3 -10F (PC100) 100 6 – 2 1.0 2 2 2/2/2 -10 (PC100) 100 – 6 2 1.0 3 3 3/3/3 Unit MHz ns ns ns ns cycles cycles 54-pin TSOP 4LC4M16S0 7/5/00 ALLIANCE SEMICONDUCTOR 1 Copyright ©2000 Alliance Semiconductor. All rights reserved. AS4LC4M16S0 AS4LC16M4S0 ® Functional description The AS4LC8M8S0 and AS4LC4M16S0 are high-performance 64-megabit CMOS Synchronous Dynamic Random Access Memory (SDRAM) devices organized as 2,097,152 words × 8 bits × 4 banks, and 1,048,576 words × 16 bits × 4 banks, respectively. Very high bandwidth is achieved using a pipelined architecture where all inputs and outputs are referenced to the rising edge of a common clock. Programmable burst mode can be used to read up to a full page of data without selecting a new column address. The four internal banks can be alternately accessed (read or write) at the maximum clock frequency for seamless interleaving operations. This provides a significant advantage over asynchronous EDO and fast page mode devices. This SDRAM product also features a programmable mode register, allowing users to select read latency as well as burst length and type (sequential or interleaved). Lower latency improves first data access in terms of CLK cycles, while higher latency improves maximum frequency of operation. This feature enables flexible performance optimization for a variety of applications. DRAM commands and functions are decoded from control inputs. Basic commands are as follows: • Deactivate all banks • Select row; activate bank • Mode register set • Deactivate bank • Deselect; power down • CBR refresh • Select column; write • Select column; read • Auto precharge with read/write • Self-refresh The 64 Mb DRAM devices are available in 400-mil plastic TSOP II packages and have 54 pins in each configuration. Both devices operate with a power supply of 3.3V ± 0.3V . Multiple power and ground pins are provided for low switching noise and EMI. Inputs and outputs are LVTTL-compatible. Logic block diagram CLK Clock generator CKE BA0, BA1 A[11:0] Bank select Row address buffer Mode register Refresh counter Command decoder CS RAS CAS WE Control logic Burst counter Data control circuit Input and output buffer Latch circuit Column address buffer Bank A† 1M×16 (4096×256×16) Bank B† 1M×16 (4096×256×16) Bank C† 1M×16 (4096×256×16) Bank D† 1M×16 (4096×256×16) Sense amplifier Column decoder and latch circuit Row decoder DQM‡ DQ † For AS4LC8M8S0, Banks A-D will read 8M×8 (4096×512×8). ‡For AS4LC4M16S0, DQM will be UDQM and LDQM. 2 ALLIANCE SEMICONDUCTOR 7/5/00 ® AS4LC8M8S0 AS4LC4M16S0 Pin descriptions Pin CLK Name System clock Description All operations synchronized to rising edge of CLK. It also increments the burst counters. Controls CLK input. If CKE is high, the ne.


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