AD9774 Interpolation Filters Datasheet

AD9774 Datasheet, PDF, Equivalent


Part Number

AD9774

Description

14-Bit/ 32 MSPS TxDAC with 4x Interpolation Filters

Manufacture

Analog Devices

Total Page 24 Pages
Datasheet
Download AD9774 Datasheet


AD9774
a
14-Bit, 32 MSPS TxDAC+™
with 4؋ Interpolation Filters
AD9774
FEATURES
Single 3 V or 5 V Supply
14-Bit DAC Resolution and Input Data Width
32 MSPS Input Data Rate at 5 V
13.5 MHz Reconstruction Bandwidth
12 ENOBS @ 1 MHz
77 dBc SFDR @ 5 MHz
4؋ Interpolation Filter
69 dB Image Rejection
84% Passband to Nyquist Ratio
0.002 dB Passband Ripple
23 3/4 Cycle Latency
Internal 4؋ Clock Multiplier
On-Chip 1.20 V Reference
44-Lead MQFP Package
APPLICATIONS
Communication Transmit Channel:
Wireless Basestations
ADSL/HFC Modems
Direct Digital Synthesis (DDS)
PRODUCT DESCRIPTION
The AD9774 is a single supply, oversampling, 14-bit digital-to-
analog converter (DAC) optimized for waveform reconstruction
applications requiring exceptional dynamic range. Manufac-
tured on an advanced CMOS process, it integrates a complete,
low distortion 14-bit DAC with a 4× digital interpolation filter
and clock multiplier. The two-stage, 4× digital interpolation
filter provides more than a six-fold reduction in the complexity
of the analog reconstruction-filter. It does so by multiplying the
input data rate by a factor of four while simultaneously suppressing
the original inband images by more than 69 dB. The on-chip
clock multiplier provides all the necessary clocks. The AD9774
can reconstruct full-scale waveforms having bandwidths as high
as 13.5 MHz when operating at an input data rate of 32 MSPS
and a DAC output rate of 128 MSPS.
The 14-bit DAC provides differential current outputs to support
differential or single-ended applications. A segmented current
source architecture is combined with a proprietary switching tech-
nique to reduce spurious components and enhance dynamic per-
formance. Matching between the two current outputs ensures
enhanced dynamic performance in a differential output configura-
tion. The differential current outputs may be fed into a transformer
or tied directly to an output resistor to provide two complementary,
single-ended voltage outputs. A differential op amp topology can
also be used to obtain a single-ended output voltage. The output
voltage compliance range is nominally 1.25 V.
TxDAC+ is a trademark of Analog Devices, Inc.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
PLL VCO PLL
CLK4؋IN PLLLOCK ENABLE IN/EXT DIVIDE
CLK IN/OUT
DATA
INPUTS
(DB13-DB0)
AD9774
PLL CLOCK
MULTIPLIER
1؋ 2؋ 4؋
14 EDGE 14
TRIGGERED
2؋
LATCHES
14
2؋
4؋
14
14-BIT
DAC
PLLCOM
LPF
PLLVDD
IOUTA
IOUTB
SNOOZE
SLEEP
+1.2V REFERENCE
AND CONTROL AMP
REFIO
FSADJ
DCOM DVDD ICOMP ACOM AVDD REFLO REFCOMP
Edge-triggered input latches, a 4× clock multiplier, and a tem-
perature compensated bandgap reference have also been inte-
grated to provide a complete monolithic DAC solution. Flexible
supply options support +3 V and +5 V CMOS logic families.
TTL logic levels can also be accommodated by reducing the
AD9774 digital supply.
The on-chip reference and control amplifier are configured for
maximum accuracy and flexibility. The AD9774 can be driven
by the on-chip reference or by a variety of external reference
voltages. The full-scale current of the AD9774 can be adjusted
over a 2 mA to 20 mA range, thus providing additional gain
ranging capabilities.
The AD9774 is available in a 44-lead MQFP package. It is
specified for operation over the industrial temperature range.
PRODUCT HIGHLIGHTS
1. On-Chip 4× interpolation filter eases analog reconstruction
filter requirements by suppressing the first three images by 69 dB.
2. Low glitch and fast settling time provide outstanding dynamic
performance for waveform reconstruction or digital synthesis
requirements, including communications.
3. On-chip, edge-triggered input CMOS latches interface readily
to CMOS and TTL logic families. The AD9774 can support
input data rates up to 32 MSPS.
4. A temperature compensated, 1.20 V bandgap reference is
included on-chip, providing a complete DAC solution. An
external reference may also be used.
5. The current output(s) of the AD9774 can easily be configured
for various single-ended or differential circuit topologies.
6. On-chip clock multiplier generates all the high-speed clocks
required by the internal interpolation filters. Both 2× and 4×
clocks are generated from the lower rate data clock supplied
by the user.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998

AD9774
AD9774–SPECIFICATIONS
DC SPECIFICATIONS (TMIN to TMAX, AVDD = +5 V, PLLVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, unless otherwise noted)
Parameter
Min Typ Max
Units
RESOLUTION
14 Bits
DC ACCURACY1
Integral Linearity Error (INL)
TA = +25°C
TMIN to TMAX
Differential Nonlinearity (DNL)
TA = +25°C
TMIN to TMAX
Monotonicity (12-Bit)
± 4 LSB
± 3 LSB
GUARANTEED OVER RATED SPECIFICATION TEMPERATURE RANGE
ANALOG OUTPUT
Offset Error
Gain Error (Without Internal Reference)
Gain Error (With Internal Reference)
Full-Scale Output Current2
Output Compliance Range
Output Resistance
Output Capacitance
–0.025
+0.025
–7 ± 1 +7
+7.5 ± 1 +7.5
20
1.25
100
5
% of FSR
% of FSR
% of FSR
mA
V
k
pF
REFERENCE OUTPUT
Reference Voltage
Reference Output Current3
1.14 1.20 1.26
1
V
µA
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance
0.1 1.25
1
V
M
TEMPERATURE COEFFICIENTS
Unipolar Offset Drift
Gain Drift (Without Internal Reference)
Gain Drift (With Internal Reference)
Reference Voltage Drift
0
± 50
± 100
± 100
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
POWER SUPPLY
AVDD
Voltage Range4
Analog Supply Current (IAVDD)
Analog Supply Current in SLEEP Mode (IAVDD)
PLLVDD
Voltage Range
Clock Multiplier Supply Current (IPLLVDD)
DVDD
Voltage Range
Digital Supply Current at 5 V (IDVDD)5
Digital Supply Current at 5 V in SNOOZE Mode (IDVDD)
Digital Supply Current at 3 V (IDVDD)5
Nominal Power Dissipation
AVDD and DVDD at 3 V6
AVDD and DVDD at 5 V6
Power Supply Rejection Ratio (PSRR)7 – AVDD
Power Supply Rejection Ratio (PSRR)7 – PLLVDD
Power Supply Rejection Ratio (PSRR)7 – DVDD
2.7
2.7
2.7
–0.2
–0.025
–0.025
5.0
26.5
3.2
5.0
13
5.0
123.0
42.0
62.0
415
1125
5.5
32
5
5.5
17
5.5
140.0
50.0
+0.2
+0.025
+0.025
V
mA
mA
V
mA
V
mA
mA
mA
mW
mW
% of FSR/V
% of FSR/V
% of FSR/V
OPERATING RANGE
–40 +85 °C
NOTES
1Measured at IOUTA driving a virtual ground.
2Nominal full-scale current, IOUTFS, is 32 × the IREF current.
3Use an external amplifier to drive any external load.
4For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance.
5Measured at fCLOCK = 25 MSPS and fOUT = 1.01 MHz.
6Measured as unbuffered voltage output into 50 RLOAD at IOUTA and IOUTB, fCLOCK = 32 MSPS and fOUT = 12.8 MHz.
7± 5% power supply variation.
Specifications subject to change without notice.
–2– REV. B


Features a FEATURES Single 3 V or 5 V Supply 14-B it DAC Resolution and Input Data Width 32 MSPS Input Data Rate at 5 V 13.5 MHz Reconstruction Bandwidth 12 ENOBS @ 1 MHz 77 dBc SFDR @ 5 MHz 4 ؋ Interpolat ion Filter 69 dB Image Rejection 84% Pa ssband to Nyquist Ratio 0.002 dB Passba nd Ripple 23 3/4 Cycle Latency Internal 4؋ Clock Multiplier On-Chip 1.20 V Re ference 44-Lead MQFP Package APPLICATIO NS Communication Transmit Channel: Wire less Basestations ADSL/HFC Modems Direc t Digital Synthesis (DDS) 14-Bit, 32 M SPS TxDAC+™ with 4؋ Interpolation Fi lters AD9774 FUNCTIONAL BLOCK DIAGRAM C LK4؋IN PLLLOCK PLL ENABLE VCO IN/EXT P LL DIVIDE PLLCOM PLL CLOCK MULTIPLIER 4 ؋ DATA INPUTS (DB13-DB0) SNOOZE SLEEP DCOM DVDD 14 EDGE TRIGGERED LATCHES AD 9774 CLK IN/OUT 1؋ 14 2؋ 2؋ 14 2؋ 4 ؋ LPF PLLVDD IOUTA IOUTB 14 14-BIT D AC +1.2V REFERENCE AND CONTROL AMP RE FIO FSADJ ICOMP ACOM AVDD REFLO REFCOM P Edge-triggered input latches, a 4× clock multiplier, and a temperature compensated bandgap reference have also .
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