AD9775 Digital-to-Analog Converter Datasheet

AD9775 Datasheet, PDF, Equivalent


Part Number

AD9775

Description

Digital-to-Analog Converter

Manufacture

Analog Devices

Total Page 30 Pages
Datasheet
Download AD9775 Datasheet


AD9775
14-Bit, 160 MSPS, 2×/4×/8× Interpolating
Dual TxDAC+® Digital-to-Analog Converter
AD9775
FEATURES
14-bit resolution, 160 MSPS/400 MSPS input/output
data rate
Selectable 2×/4×/8× interpolating filter
Programmable channel gain and offset adjustment
fS/4, fS/8 digital quadrature modulation capability
Direct IF transmission mode for 70 MHz + IFs
Enables image rejection architecture
Fully compatible SPI® port
Excellent ac performance
SFDR: −71 dBc @ 2 MHz to 35 MHz
W-CDMA ACPR: −71 dB @ IF = 19.2 MHz
Internal PLL clock multiplier
Selectable internal clock divider
Versatile clock input
Differential/single-ended sine wave or TTL/CMOS/LVPECL
compatible
Versatile input data interface
Twos complement/straight binary data coding
Dual-port or single-port interleaved input data
Single 3.3 V supply operation
Power dissipation: 1.2 W @ 3.3 V typical
On-chip, 1.2 V reference
80-lead, thin quad flat package, exposed pad (TQFP_EP)
APPLICATIONS
Communications
Analog quadrature modulation architecture
3G, multicarrier GSM, TDMA, CDMA systems
Broadband wireless, point-to-point microwave radios
Instrumentation/ATE
FUNCTIONAL BLOCK DIAGRAM
AD9775
14
I AND Q
NONINTERLEAVED
OR INTERLEAVED
DATA
14
DATA
ASSEMBLER
HALF-
BAND
FILTER1*
I 16
LATCH
16
HALF- HALF-
BAND BAND
FILTER2* FILTER3*
16 16
Q 16
LATCH
16
16 16
COS
SIN
fDAC/2, 4, 8
SIN
IMAGE
REJECTION/
DUAL DAC
MODE
BYPASS
MUX
WRITE
SELECT
MUX
CONTROL
CLOCK OUT
/2
SPI INTERFACE AND
CONTROL REGISTERS
/2
/2
* HALF-BAND FILTERS ALSO CAN BE
CONFIGURED FOR ZERO STUFFING ONLY
FILTER
BYPASS
MUX
/2
COS
(fDAC)
PRESCALER
PHASE DETECTOR
AND VCO
PLL CLOCK MULTIPLIER AND CLOCK DIVIDER
Figure 1.
IDAC
GAIN
DAC
OFFSET
DAC
I/Q DAC
GAIN/OFFSET
REGISTERS
IDAC
IOUT
DIFFERENTIAL
CLK
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.

AD9775
AD9775
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
General Description ......................................................................... 4
Product Highlights ....................................................................... 4
Specifications..................................................................................... 5
DC Specifications ......................................................................... 5
Dynamic Specifications ............................................................... 6
Digital Specifications ................................................................... 7
Digital Filter Specifications ......................................................... 8
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Thermal Resistance ...................................................................... 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 12
Terminology .................................................................................... 17
Mode Control (via SPI Port) ......................................................... 18
Register Descriptions ..................................................................... 19
Address 0x00 ............................................................................... 19
Address 0x01 ............................................................................... 19
Address 0x02 ............................................................................... 19
Address 0x03 ............................................................................... 20
Address 0x04 ............................................................................... 20
Address 0x05, Address 0x09 ..................................................... 20
Address 0x06, Address 0x0A..................................................... 20
Address 0x07, Address 0x0B ..................................................... 20
Address 0x08, Address 0x0C..................................................... 20
Address 0x08, Address 0x0C..................................................... 20
Functional Description .................................................................. 21
Serial Interface for Register Control ........................................ 21
General Operation of the Serial Interface ............................... 21
Instruction Byte .......................................................................... 22
Serial Interface Port Pin Descriptions ..................................... 22
MSB/LSB Transfers..................................................................... 22
Notes on Serial Port Operation ................................................ 22
DAC Operation........................................................................... 24
1R/2R Mode ................................................................................ 25
Clock Input Configurations...................................................... 25
Programmable PLL .................................................................... 26
Power Dissipation....................................................................... 27
Sleep/Power-Down Modes........................................................ 28
Two-Port Data Input Mode ...................................................... 28
PLL Enabled, Two-Port Mode .................................................. 28
DATACLK Inversion.................................................................. 29
DATACLK Driver Strength....................................................... 29
PLL Enabled, One-Port Mode .................................................. 29
ONEPORTCLK Inversion......................................................... 29
ONEPORTCLK Driver Strength.............................................. 30
IQ Pairing .................................................................................... 30
PLL Disabled, Two-Port Mode................................................. 30
PLL Disabled, One-Port Mode ................................................. 30
Digital Filter Modes ................................................................... 31
Amplitude Modulation.............................................................. 31
Modulation, No Interpolation .................................................. 32
Modulation, Interpolation = 2× ............................................... 33
Modulation, Interpolation = 4× ............................................... 34
Modulation, Interpolation = 8× ............................................... 35
Zero Stuffing ............................................................................... 36
Interpolating (Complex Mix Mode)........................................ 36
Operations on Complex Signals............................................... 36
Complex Modulation and Image Rejection of Baseband
Signals .......................................................................................... 37
Image Rejection and Sideband Suppression of Modulated
Carriers ........................................................................................ 38
Applying the Output Configurations........................................... 42
Unbuffered Differential Output, Equivalent Circuit ............. 42
Differential Coupling Using a Transformer............................ 42
Differential Coupling Using an Op Amp................................ 43
Interfacing the AD9775 with the AD8345 Quadrature
Modulator.................................................................................... 43
Evaluation Board ............................................................................ 44
Outline Dimensions ....................................................................... 54
Ordering Guide .......................................................................... 54
Rev. E | Page 2 of 56


Features 14-Bit, 160 MSPS, 2×/4×/8× Interpolat ing Dual TxDAC+® Digital-to-Analog Con verter AD9775 FEATURES 14-bit resoluti on, 160 MSPS/400 MSPS input/output data rate Selectable 2×/4×/8× interpolat ing filter Programmable channel gain an d offset adjustment fS/4, fS/8 digital quadrature modulation capability Direct IF transmission mode for 70 MHz + IFs Enables image rejection architecture Fu lly compatible SPI® port Excellent ac performance SFDR: −71 dBc @ 2 MHz to 35 MHz W-CDMA ACPR: −71 dB @ IF = 19. 2 MHz Internal PLL clock multiplier Sel ectable internal clock divider Versatil e clock input Differential/single-ended sine wave or TTL/CMOS/LVPECL compatibl e Versatile input data interface Twos complement/straight binary data coding Dual-port or single-port interleaved in put data Single 3.3 V supply operation Power dissipation: 1.2 W @ 3.3 V typica l On-chip, 1.2 V reference 80-lead, thi n quad flat package, exposed pad (TQFP_ EP) APPLICATIONS Communications Analog quadrature modulation architecture 3.
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