AD9777 D/A Converter Datasheet

AD9777 Datasheet, PDF, Equivalent


Part Number

AD9777

Description

Interpolating Dual TxDAC+ D/A Converter

Manufacture

Analog Devices

Total Page 30 Pages
Datasheet
Download AD9777 Datasheet


AD9777
16-Bit, 160 MSPS 2x/4x/8x
Interpolating Dual TxDAC+® D/A Converter
AD9777
FEATURES
16-bit resolution, 160 MSPS/400 MSPS input/output
data rate
Selectable 2×/4×/8× interpolating filter
Programmable channel gain and offset adjustment
fS/4, fS/8 digital quadrature modulation capability
Direct IF transmission mode for 70 MHz + IFs
Enables image rejection architecture
Fully compatible SPI® port
Excellent ac performance
SFDR −73 dBc @ 2 MHz to 35 MHz
WCDMA ACPR 71 dB @ IF = 19.2 MHz
Internal PLL clock multiplier
Selectable internal clock divider
Versatile clock input
Differential/single-ended sine wave or
TTL/CMOS/LVPECL compatible
Versatile input data interface
Twos complement/straight binary data coding
Dual-port or single-port interleaved input data
Single 3.3 V supply operation
Power dissipation: typical 1.2 W @ 3.3 V
On-chip 1.2 V reference
80-lead thin quad flat package, exposed pad (TQFP_EP)
APPLICATIONS
Communications
Analog quadrature modulation architecture
3G, multicarrier GSM, TDMA, CDMA systems
Broadband wireless, point-to-point microwave radios
Instrumentation/ATE
FUNCTIONAL BLOCK DIAGRAM
AD9777
16
I AND Q
NONINTERLEAVED
OR INTERLEAVED
DATA
16
DATA
ASSEMBLER
HALF-
BAND
FILTER1*
I 16
LATCH
16
HALF- HALF-
BAND
BAND
FILTER2* FILTER3*
16 16
Q 16
LATCH
16
16 16
COS
SIN
fDAC/2, 4, 8
SIN
IMAGE
REJECTION/
DUAL DAC
MODE
BYPASS
MUX
WRITE
SELECT
MUX
CONTROL
CLOCK OUT
/2
SPI INTERFACE AND
CONTROL REGISTERS
/2
/2
* HALF-BAND FILTERS ALSO CAN BE
CONFIGURED FOR ZERO STUFFING ONLY
FILTER
BYPASS
MUX
/2
COS
(fDAC)
PRESCALER
PHASE DETECTOR
AND VCO
PLL CLOCK MULTIPLIER AND CLOCK DIVIDER
Figure 1.
IDAC
GAIN
DAC
OFFSET
DAC
I/Q DAC
GAIN/OFFSET
REGISTERS
IDAC
IOUT
DIFFERENTIAL
CLK
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
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Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2006 Analog Devices, Inc. All rights reserved.

AD9777
AD9777* Product Page Quick Links
Last Content Update: 11/01/2016
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Documentation
Application Notes
• AN-137: A Digitally Programmable Gain and Attenuation
Amplifier Design
• AN-237: Choosing DACs for Direct Digital Synthesis
• AN-302: Exploit Digital Advantages in an SSB Receiver
• AN-320A: CMOS Multiplying DACs and Op Amps
Combine to Build Programmable Gain Amplifier, Part 1
• AN-320B: CMOS Multiplying DACs and Op Amps
Combine to Build Programmable Gain Amplifiers, Part 2
• AN-595: Understanding Pin Compatibility in the TxDAC®
Line of High Speed D/A Converters
• AN-640: Synchronizing Multiple AD9777s Using
DATACLK Input Mode
• AN-642: Coupling a Single-Ended Clock Source to the
Differential Clock Input of Third-Generation TxDAC® and
TxDAC+® Products
• AN-748: Set-Up and Hold Measurements in High Speed
CMOS Input DACs
• AN-808: Multicarrier CDMA2000 Feasibility
• AN-912: Driving a Center-Tapped Transformer with a
Balanced Current-Output DAC
Data Sheet
• AD9777: 16-Bit 160 MSPS 2x/4x/8x Interpolating Dual
TxDAC+® D/A Converter Data Sheet
Tools and Simulations
• AD9777 IBIS Models
Reference Materials
Informational
• Advantiv™ Advanced TV Solutions
Solutions Bulletins & Brochures
• Digital to Analog Converters ICs Solutions Bulletin
Design Resources
• AD9777 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
Discussions
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Sample and Buy
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Technical Support
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Features 16-Bit, 160 MSPS 2x/4x/8x Interpolating Dual TxDAC+® D/A Converter AD9777 FEA TURES 16-bit resolution, 160 MSPS/400 M SPS input/output data rate Selectable 2 ×/4×/8× interpolating filter Program mable channel gain and offset adjustmen t fS/4, fS/8 digital quadrature modulat ion capability Direct IF transmission m ode for 70 MHz + IFs Enables image reje ction architecture Fully compatible SPI ® port Excellent ac performance SFDR 73 dBc @ 2 MHz to 35 MHz WCDMA ACPR 7 1 dB @ IF = 19.2 MHz Internal PLL clock multiplier Selectable internal clock d ivider Versatile clock input Differenti al/single-ended sine wave or TTL/CMOS/L VPECL compatible Versatile input data interface Twos complement/straight bina ry data coding Dual-port or single-port interleaved input data Single 3.3 V su pply operation Power dissipation: typic al 1.2 W @ 3.3 V On-chip 1.2 V referenc e 80-lead thin quad flat package, expos ed pad (TQFP_EP) APPLICATIONS Communica tions Analog quadrature modulation architecture 3G, multicarrie.
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