AD9801 Electronic Cameras Datasheet

AD9801 Datasheet, PDF, Equivalent


Part Number

AD9801

Description

CCD Signal Processor For Electronic Cameras

Manufacture

Analog Devices

Total Page 12 Pages
Datasheet
Download AD9801 Datasheet


AD9801
a
FEATURES
10-Bit, 18 MSPS A/D Converter
18 MSPS Full-Speed CDS
Low Noise, Wideband PGA
Internal Voltage Reference
No Missing Codes Guaranteed
+3 V Single Supply Operation
Low Power CMOS: 185 mW
48-Pin TQFP Package
CCD Signal Processor
For Electronic Cameras
AD9801
FUNCTIONAL BLOCK DIAGRAM
PBLK
19
PIN 27
DIN 26
CLPDM PGACONT1 PGACONT2 SHP SHD ADCCLK
23 29
30 21 22 16
CLAMP
TIMING
GENERATOR
CDS
PGA
S/H
A/D
10 2
DOUT
11
REFERENCE
CLAMP
AD9801 12 DRVDD
37 48 47 18
CMLEVEL VRT VRB STBY
20 33 43
CLPOB ACVDD ADVDD
17
DVDD
PRODUCT DESCRIPTION
The AD9801 is a complete CCD signal processor developed for
electronic cameras. It is well suited for both video conferencing
and consumer level still camera applications.
The signal processing chain is comprised of a high speed CDS,
variable gain PGA and 10-bit ADC. Required clamping
circuitry and an onboard voltage reference are also provided.
The AD9801 operates from a single +3 V supply with a typical
power consumption of 185 mW.
The AD9801 is packaged in a space saving 48-pin thin-quad
flatpack (TQFP) and is specified over an operating temperature
range of 0°C to +70°C.
PRODUCT HIGHLIGHTS
1. On-Chip Input Clamp and CDS
Clamp circuitry and high speed correlated double sampler
allow for simple ac coupling to interface a CCD sensor at full
18 MSPS conversion rate.
2. On-Chip PGA
The AD9801 includes a low noise, wideband amplifier with
analog variable gain from 0 dB to 31.5 dB (linear in dB).
3. 10-Bit, High Speed A/D Converter
A linear 10-bit ADC is capable of digitizing CCD signals at
the full 18 MSPS conversion rate. (Typical DNL is ± 0.5 LSB
and no missing code performance is guaranteed.)
4. Low Power
At 185 mW, the AD9801 consumes a fraction of the power of
presently available multichip solutions. The part’s power-
down mode (15 mW) further enhances its desirability in low
power, battery operated applications.
5. Digital I/O Functionality
The AD9801 offers three-state digital output control.
6. Small Package
Packaged in a 48-pin, surface-mount thin-quad flatpack, the
AD9801 is well suited to very tight, low headroom designs.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997

AD9801
AD9801–SPECIFICATIONS (TMIN to TMAX with ACVDD = 3.15 V, ADVDD = 3.15 V, DVDD = 3.15 V, DRVDD = 3.15 V unless
otherwise noted)
Parameter
Min Typ Max
Units
TEMPERATURE RANGE
Operating
Storage
0
–65
70 °C
150 °C
POWER SUPPLY VOLTAGE
(For Functional Operation)
ACVDD
ADVDD
DVDD
DRVDD
3.00 3.15 3.50
3.00 3.15 3.50
3.00 3.15 3.50
3.00 3.15 3.50
V
V
V
V
POWER SUPPLY CURRENT
ACVDD
ADVDD
DVDD
DRVDD
39.5 mA
14.6 mA
4.7 mA
0.07 mA
POWER CONSUMPTION
Normal Operation
Power-Down Mode
185 mW
15 mW
MAXIMUM SHP, SHD, ADCCLK RATE
18
MHz
ADC
Resolution
Differential Nonlinearity
No Missing Codes
ADCCLK Rate
Reference Top Voltage
Reference Bottom Voltage
Input Range
10
± 0.5
GUARANTEED
18
1.75
1.25
1.0
Bits
LSB
MHz
V
V
V p-p
CDS
Maximum Input Signal
Pixel Rate
500
mV p-p
18 MHz
PGA1
Maximum Gain
High Gain
Medium Gain
Minimum Gain
31.5
15 19 23
0.5 3.5 6.5
–5 –1 +3
dB
dB
dB
dB
CLAMP
Average Black Level (During CLPOB. Only
Stable Over PGA Range 0.3 V to 2.7 V)
32
LSB
1PGA test conditions: max gain PGACONT1 = 2.7 V, PGACONT2 = 1.5 V; high gain PGACONT1 = 2.0 V, PGACONT2 = 1.5 V; medium gain PGACONT1 =
0.5 V, PGACONT2 = 1.5 V; minimum gain PGACONT1 = 0.3 V, PGACONT2 = 1.5 V.
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS (TMIN to TMAX with ACVDD = 3.15 V, ADVDD = 3.15 V, DVDD = 3.15 V, DRVDD = 3.15 V unless otherwise noted)
Parameter
Symbol
Min
Typ Max
Units
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
VIH
VIL
IIH
IIL
CIN
2.4
0.6
10
10
10
V
V
µA
µA
pF
LOGIC OUTPUTS
High Level Output Voltage
VOH
2.4
Low Level Output Voltage
VOL
IOH
IOL
0.6
50
50
V
V
µA
µA
Specifications subject to change without notice.
–2– REV. 0


Features a FEATURES 10-Bit, 18 MSPS A/D Converter 18 MSPS Full-Speed CDS Low Noise, Wide band PGA Internal Voltage Reference No Missing Codes Guaranteed +3 V Single Su pply Operation Low Power CMOS: 185 mW 4 8-Pin TQFP Package PBLK 19 CCD Signal Processor For Electronic Cameras AD9801 FUNCTIONAL BLOCK DIAGRAM CLPDM 23 PGA CONT1 PGACONT2 29 30 SHP SHD ADCCLK 21 22 16 CLAMP PIN 27 CDS DIN 26 CLAMP R EFERENCE 37 48 47 18 20 33 TIMING GENE RATOR PGA S/H A/D 10 2 DOUT 11 AD9801 43 17 12 DRVDD CMLEVEL VRT VRB STBY CLPOB ACVDD ADVDD DVDD PRODUCT DE SCRIPTION PRODUCT HIGHLIGHTS The AD98 01 is a complete CCD signal processor d eveloped for electronic cameras. It is well suited for both video conferencing and consumer level still camera applic ations. The signal processing chain is comprised of a high speed CDS, variable gain PGA and 10-bit ADC. Required clam ping circuitry and an onboard voltage r eference are also provided. The AD9801 operates from a single +3 V supply with a typical power consump.
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