and Sample/Hold. ADC10062 Datasheet

ADC10062 Sample/Hold. Datasheet pdf. Equivalent

ADC10062 Datasheet
Recommendation ADC10062 Datasheet
Part ADC10062
Description 10-Bit 600 ns A/D Converter with Input Multiplexer and Sample/Hold
Feature ADC10062; ADC10061/ADC10062/ADC10064 10-Bit 600 ns A/D Converter with Input Multiplexer and Sample/Hold June .
Manufacture National Semiconductor
Datasheet
Download ADC10062 Datasheet




National Semiconductor ADC10062
June 1999
ADC10061/ADC10062/ADC10064
10-Bit 600 ns A/D Converter with Input Multiplexer and
Sample/Hold
General Description
Using an innovative, patented multistep* conversion tech-
nique, the 10-bit ADC10061, ADC10062, and ADC10064
CMOS analog-to-digital converters offer sub-microsecond
conversion times yet dissipate a maximum of only 235 mW.
The ADC10061, ADC10062, and ADC10064 perform a
10-bit conversion in two lower-resolution “flashes”, thus
yielding a fast A/D without the cost, power dissipation, and
other problems associated with true flash approaches. The
ADC10061 is pin-compatible with the ADC1061 but much
faster, thus providing a convenient upgrade path for the
ADC1061.
The analog input voltage to the ADC10061, ADC10062, and
ADC10064 is sampled and held by an internal sampling cir-
cuit. Input signals at frequencies from dc to over 200 kHz
can therefore be digitized accurately without the need for an
external sample-and-hold circuit.
The ADC10062 and ADC10064 include a “speed-up” pin.
Connecting an external resistor between this pin and ground
reduces the typical conversion time to as little as 350 ns with
only a small increase in linearity error.
For ease of interface to microprocessors, the ADC10061,
ADC10062, and ADC10064 have been designed to appear
as a memory location or I/O port without the need for exter-
nal interface logic.
*U.S. Patent Number 4918449
Features
n Built-in sample-and-hold
n Single +5V supply
n 1, 2, or 4-input multiplexer options
n No external clock required
n Speed adjust pin for faster conversions (ADC10062
and ADC10064). See ADC10662/4 for high speed
guaranteed performance.
Key Specifications
n Conversion time to 10 bits
600 ns typical,
n 900 ns max over temperature
n Sampling Rate
800 kHz
n Low power dissipation
235 mW (max)
n Total unadjusted error
±1.0 LSB (max)
n No missing codes over temperature
Applications
n Digital signal processor front ends
n Instrumentation
n Disk drives
n Mobile telecommunications
Simplified Block Diagram
*ADC10061 Only
**ADC10062 and ADC10064 Only
***ADC10064 Only
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS011020
DS011020-1
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National Semiconductor ADC10062
Ordering Information
Industrial (−40˚C TA +85˚C)
ADC10061CIWM
ADC10062CIWM
ADC10064CIWM
Connection Diagrams
Package
M20B Small Outline
M24B Small Outline
M28B Small Outline
Top View
DS011020-11
Top View
DS011020-12
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Top View
DS011020-13
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National Semiconductor ADC10062
Pin Descriptions
DVCC, AVCC These are the digital and analog positive sup-
ply voltage inputs. They should always be con-
nected to the same voltage source, but are
brought out separately to allow for separate
bypass capacitors. Each supply pin should be
bypassed with a 0.1 µF ceramic capacitor in
parallel with a 10 µF tantalum capacitor to
ground.
INT This is the active low interrupt output. INT
goes low at the end of each conversion, and
returns to a high state following the rising edge
of RD.
S/H This is the Sample/Hold control input. When
this pin is forced low (and CS is low), it causes
the analog input signal to be sampled and ini-
tiates a new conversion.
RD This is the active low Read control input.
When this RD and CS are low, any data
present in the output registers will be placed
on the data bus.
CS This is the active low Chip Select control input.
When low, this pin enables the RD and S/H
pins.
S0, S1
On the multiple-input devices (ADC10062 and
ADC10064), these pins select the analog input
that will be connected to the A/D during the
conversion. The input is selected based on the
state of S0 and S1 when S/H makes its
High-to-Low transition (See the Timing Dia-
grams). The ADC10064 includes both S0 and
S1. The ADC10062 includes just S0, and the
ADC10061 includes neither.
VREF−,
VREF+
These are the reference voltage inputs. They
may be placed at any voltage between GND
and VCC, but VREF+ must be greater than
VREF−. An input voltage equal to VREF− pro-
duces an output code of 0, and an input volt-
age equal to (VREF+ − 1 LSB) produces an out-
put code of 1023.
VIN, VIN0,
VIN1, VIN2,
VIN3
These are the analog input pins. The
ADC10061 has one input (VIN), the ADC10062
has two inputs (VIN0 and VIN1), and the
ADC10064 has four inputs (VIN0, VIN1, VIN2
and VIN3). The impedance of the source
should be less than 500for best accuracy
and conversion speed. For accurate conver-
sions, no input pin (even one that is not se-
lected) should be driven more than 50 mV
above VCC or 50 mV below ground.
GND, AGND, These are the power supply ground pins. The
DGND
ADC10061 has a single ground pin (GND),
and the ADC10062 and ADC10064 have
separate analog and digital ground pins
(AGND and DGND) for separate bypassing of
the analog and digital supplies. The ground
pins should be connected to a stable,
noise-free system ground. For the devices
with two ground pins, both pins should be re-
turned to the same potential.
DB0–DB9 These are the TRI-STATE® output pins.
SPEED ADJ (ADC10062 and ADC10064 only). This pin is
normally left unconnected, but by connecting a
resistor between this pin and ground, the con-
version time can be reduced. See the Typical
Performance Curves and the table of Electri-
cal Characteristics.
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