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ADC1061 Dataheets PDF



Part Number ADC1061
Manufacturers National Semiconductor
Logo National Semiconductor
Description 10-Bit High-Speed P-Compatible A/D Converter
Datasheet ADC1061 DatasheetADC1061 Datasheet (PDF)

ADC1061 10-Bit High-Speed µP-Compatible A/D Converter with Track/Hold Function June 1999 ADC1061 10-Bit High-Speed µP-Compatible A/D Converter with Track/Hold Function General Description Using a modified half-flash conversion technique, the 10-bit ADC1061 CMOS analog-to-digital converter offers very fast conversion times yet dissipates a maximum of only 235 mW. The ADC1061 performs a 10-bit conversion in two lower-resolution “flashes”, thus yielding a fast A/D without the cost, power dissipat.

  ADC1061   ADC1061


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ADC1061 10-Bit High-Speed µP-Compatible A/D Converter with Track/Hold Function June 1999 ADC1061 10-Bit High-Speed µP-Compatible A/D Converter with Track/Hold Function General Description Using a modified half-flash conversion technique, the 10-bit ADC1061 CMOS analog-to-digital converter offers very fast conversion times yet dissipates a maximum of only 235 mW. The ADC1061 performs a 10-bit conversion in two lower-resolution “flashes”, thus yielding a fast A/D without the cost, power dissipation, and other problems associated with true flash approaches. The analog input voltage to the ADC1061 is tracked and held by an internal sampling circuit. Input signals at frequencies from DC to greater than 160 kHz can therefore be digitized accurately without the need for an external sample-and-hold circuit. For ease of interface to microprocessors, the ADC1061 has been designed to appear as a memory location or I/O port without the need for external interface logic. Features n n n n n n 1.8 µs maximum conversion time to 10 bits Low power dissipation: 235 mW (maximum) Built-in track-and-hold No external clock required Single +5V supply No missing codes over temperature Applications n n n n Waveform digitizers Disk drives Digital signal processor front ends Mobile telecommunications Simplified Block and Connection Diagrams DS010559-2 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS010559 www.national.com Simplified Block and Connection Diagrams (Continued) Dual-In-Line Package DS010559-1 Top View Order Number ADC1061CIN or ADC1061CIWM See NS Package J20A, M20B or N20A Ordering Information Industrial (−40˚C ≤ TA ≤ 85˚C) ADC1061CIN ADC1061CIWM Package N20A M20B Pin Descriptions Symbol DVCC, AVCC (1, 6) INT (2) S /H (3) RD (4) Function These are the digital and analog positive supply voltage inputs. They should always be connected to the same voltage source, but are brought out separately to allow for separate bypass capacitors. Each supply pin should be bypassed with a 0.1 µF ceramic capacitor in parallel with a 10 µF tantalum capacitor. This is the active low interrupt output. INT goes low at the end of each conversion, and returns to a high state following the rising edge of RD . This is the Sample/Hold control input. When this pin is forced low, it causes the analog input signal to be sampled and initiates a new conversion. This is the active low Read control input. When this pin is low, any data present in the ADC1061’s output registers will be placed on the data bus. In Mode 2, the Read signal must be low until INT goes low. Until INT goes low, the data at the output pins will be incorrect. This is the active low Chip Select control input. This pin enables the S /H and RD inputs. These are the reference voltage inputs. They may be placed at any voltage between GND − 50 mV and VCC + 50 mV, but VREF+ must be greater than VREF−. An input voltage equal to VREF− produces an output code of 0, and an input voltage equal to VREF+ − 1LSB produces an output code of 1023. This is the analog input pin. The impedance of the source should be less than 500Ω for best accuracy and conversion speed. To avoid damage to the ADC1061, VIN should not be allowed to extend beyond the power supply voltages by more than 300 mV unless the drive current is limited. For accurate conversions, VIN should not extend more than 50 mV beyond the supply voltages. This is the power supply ground pin. The ground pin should be connected to a “clean” ground reference point. These are the TRI-STATE output pins. CS (5) VREF−, VREF+ (7, 9) VIN (8) GND (10) DB0–DB9 (11-20) www.national.com 2 Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V+ = AVCC = DVCC) Voltage at any Input or Output Input Current at Any Pin (Note 3) Package Input Current (Note 3) Power Dissipation (Note 4) ESD Susceptibility (Note 5) Soldering Information (Note 6) N Package (10 seconds) −0.3V to +6V −0.3V to V+ +0.3V 5 mA 20 mA 875 mW 1500V 260˚C J Package (10 seconds) SO Package (Note 6) Vapor Phase (60 seconds) Infrared (15 seconds) Junction Temperature, TJ Storage Temperature Range 300˚C 215˚C 220˚C +150˚C −65˚C to +150˚C (Notes 1, 2) TMIN ≤ TA ≤ TMAX −40˚C ≤ TA ≤ +85˚C 4.5V to 5.5V Operating Ratings Temperature Range ADC1061CIN, ADC1061CIWM Supply Voltage Range Converter Characteristics The following specifications apply for V+ = +5V, VREF(+) = 5V, and VREF(−) = GND unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. Symbol Resolution Total Unadjusted Error Integral Linearity Error Differential Linearity Error Offset Error Fullscale Error RREF RREF VREF(+) VREF(−) VREF(+) VREF(−) VIN VIN Reference Resistance Reference Resistance VREF(+) Input Voltage VREF(−) Input .


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