and Sample/Hold. ADC10664 Datasheet

ADC10664 Sample/Hold. Datasheet pdf. Equivalent

ADC10664 Datasheet
Recommendation ADC10664 Datasheet
Part ADC10664
Description 10-Bit 360 ns A/D Converter with Input Multiplexer and Sample/Hold
Feature ADC10664; ADC10662/ADC10664 10-Bit 360 ns A/D Converter with Input Multiplexer and Sample/Hold June 1999 ADC.
Manufacture National Semiconductor
Datasheet
Download ADC10664 Datasheet




National Semiconductor ADC10664
June 1999
ADC10662/ADC10664
10-Bit 360 ns A/D Converter with Input Multiplexer and
Sample/Hold
General Description
Using an innovative, patented multistep* conversion tech-
nique, the 10-bit ADC10662 and ADC10664 are 2- and
4-input CMOS analog-to-digital converters offering
sub-microsecond conversion times yet dissipating a maxi-
mum of only 235 mW. The ADC10662 and ADC10664 per-
form a 10-bit conversion in two lower-resolution “flashes”,
thus yielding a fast A/D without the cost, power dissipation,
and other problems associated with true flash approaches.
In addition to standard static performance specifications
(Linearity, Full-Scale Error, etc.) dynamic performance (THD,
S/N) is guaranteed.
The analog input voltage to the ADC10662 and ADC10664 is
sampled and held by an internal sampling circuit. Input sig-
nals at frequencies from dc to over 250 kHz can therefore be
digitized accurately without the need for an external
sample-and-hold circuit.
The ADC10662 and ADC10664 include a “speed-up” pin.
Connecting an external resistor between this pin and ground
reduces the typical conversion time to as little as 360 ns.
For ease of interface to microprocessors, the ADC10662 and
ADC10664 have been designed to appear as a memory lo-
cation or I/O port without the need for external interface
logic.
Features
n Built-in sample-and-hold
n Single +5V supply
n 2- or 4-input multiplexer options
n No external clock required
Key Specifications
n Conversion time to 10 bits: 360 ns typical, 466 ns
max over temperature
n Sampling Rate: 1.5 MHz (min)
n Low power dissipation: 235 mW (max)
n Total harmonic distortion (50 kHz): −60 dB (max)
n No missing codes over temperature
Applications
n Digital signal processor front ends
n Instrumentation
n Disk drives
n Mobile telecommunications
Ordering Information
ADC10662
Industrial
(−40˚C TA +85˚C)
ADC10662CIWM
Package
M24B Small Outline
ADC10664
Industrial
(−40˚C TA +85˚C)
ADC10664CIWM
Package
M28B Small Outline
*U.S. Patent Number 4918449
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS011192
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National Semiconductor ADC10664
Simplified Block Diagram
*ADC10664 Only
Connection Diagrams
DS011192-9
Top View
DS011192-10
Top View
DS011192-11
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National Semiconductor ADC10664
Pin Descriptions
DVCC,
AVCC
INT
S /H
RD
CS
S0, S1
VREF−,
VREF+
These are the digital and analog positive sup-
ply voltage inputs. They should always be con-
nected to the same voltage source, but are
brought out separately to allow for separate
bypass capacitors. Each supply pin should be
bypassed with a 0.1 µF ceramic capacitor in
parallel with a 10 µF tantalum capacitor to
ground.
This is the active low interrupt output. INT
goes low at the end of each conversion, and
returns to a high state following the rising edge
of RD .
This is the Sample/Hold control input. When
this pin is forced low (and CS is low), it causes
the analog input signal to be sampled and ini-
tiates a new conversion.
This is the active low Read control input.
When this RD and CS are low, any data
present in the output registers will be placed
on the data bus.
This is the active low Chip Select control input.
When low, this pin enables the RD and S /H
pins.
These pins select the analog input that will be
connected to the A/D during the conversion.
The input is selected based on the state of S0
and S1 when S /H makes its High-to-Low tran-
sition (See the Timing Diagrams). The
ADC10664 includes both S0 and S1. The
ADC10662 includes just S0.
These are the reference voltage inputs. They
may be placed at any voltage between GND
and VCC, but VREF+ must be greater than
VREF−. An input voltage equal to VREF− pro-
duces an output code of 0, and an input volt-
age equal to (VREF+ − 1 LSB) produces an out-
put code of 1023.
VIN0, VIN1,
VIN2, VIN3
These are the analog input pins. The
ADC10662 has two inputs (VIN0 and VIN1) and
the ADC10664 has four inputs (VIN0, VIN1,
VIN2 and VIN3). The impedance of the source
should be less than 500for best accuracy
and conversion speed. For accurate conver-
sions, no input pin (even one that is not se-
lected) should be driven more than 50 mV
above VCC or 50 mV below ground.
GND, AGND, These are the power supply ground pins. The
DGND
ADC10662 and ADC10664 have separate
analog and digital ground pins (AGND and
DGND) for separate bypassing of the analog
and digital supplies. The ground pins should
be connected to a stable, noise-free system
ground. Both pins should be returned to the
same potential.
DB0–DB9 These are the TRI-STATE output pins.
SPEED
ADJ
By connecting a resistor between this pin and
ground, the conversion time can be reduced.
The specifications listed in the table of Electri-
cal Characteristics apply for a speed adjust re-
sistor (RSA) equal to 14.0 k(Mode 1) or 8.26
k(Mode 2). See the Typical Performance
Curves and the table of Electrical Characteris-
tics.
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