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ADC1230 Dataheets PDF



Part Number ADC1230
Manufacturers National Semiconductor
Logo National Semiconductor
Description Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters
Datasheet ADC1230 DatasheetADC1230 Datasheet (PDF)

ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold July 1999 ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold General Description The ADC12030, and ADC12H030 families are 12-bit plus sign successive approximation A/D converters with serial I/O and configurable input multipl.

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ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold July 1999 ADC12H030/ADC12H032/ADC12H034/ADC12H038, ADC12030/ADC12032/ADC12034/ADC12038 Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold General Description The ADC12030, and ADC12H030 families are 12-bit plus sign successive approximation A/D converters with serial I/O and configurable input multiplexers. The ADC12032/ ADC12H032, ADC12034/ADC12H034 and ADC12038/ ADC12H038 have 2, 4 and 8 channel multiplexers, respectively. The differential multiplexer outputs and A/D inputs are available on the MUXOUT1, MUXOUT2, A/DIN1 and A/DIN2 pins. The ADC12030/ADC12H030 has a two channel multiplexer with the multiplexer outputs and A/D inputs internally connected. The ADC12030 family is tested with a 5 MHz clock, while the ADC12H030 family is tested with an 8 MHz clock. On request, these A/Ds go through a self calibration process that adjusts linearity, zero and full-scale errors to less than ± 1 LSB each. The analog inputs can be configured to operate in various combinations of single-ended, differential, or pseudo-differential modes. A fully differential unipolar analog input range (0V to +5V) can be accommodated with a single +5V supply. In the differential modes, valid outputs are obtained even when the negative inputs are greater than the positive because of the 12-bit plus sign output data format. The serial I/O is configured to comply with the NSC MICROWIRE™. For voltage references see the LM4040 or LM4041. Features Serial I/O (MICROWIRE Compatible) 2, 4, or 8 channel differential or single-ended multiplexer Analog input sample/hold function Power down mode Variable resolution and conversion rate Programmable acquisition time Variable digital output word length and format No zero or full scale adjustment required Fully tested and guaranteed with a 4.096V reference 0V to 5V analog input range with single 5V power supply n No Missing Codes over temperature n n n n n n n n n n Key Specifications n Resolution n 12-bit plus sign conversion time — ADC12H030 family — ADC12030 family n 12-bit plus sign throughput time — ADC12H030 family — ADC12030 family n Integral linearity error n Single supply n Power dissipation — Power down 12-bit plus sign 5.5 µs (max) 8.8 µs (max) 8.6 µs (max) 14 µs (max) ± 1 LSB (max) 5V ± 10% 33 mW (max) 100 µW (typ) Applications n Medical instruments n Process control systems n Test equipment TRI-STATE ® is a registered trademark of National Semiconductor Corporation. COPS™ microcontrollers, HPC™ and MICROWIRE™ are trademarks of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS011354 www.national.com ADC12038 Simplified Block Diagram DS011354-1 Connection Diagrams 16-Pin Wide Body SO Packages 20-Pin Wide Body SO Packages DS011354-6 Top View DS011354-7 Top View www.national.com 2 Connection Diagrams (Continued) 28-Pin Wide Body SO Packages 24-Pin Wide Body SO Packages DS011354-8 DS011354-9 Top View Top View Ordering Information Industrial Temperature Range −40˚C ≤ TA ≤ +85˚C ADC12H030CIWM, ADC12030CIWM ADC12H032CIWM, ADC12032CIWM ADC12H034CIN, ADC12034CIN ADC12H034CIWM, ADC12034CIWM ADC12H038CIWM, ADC12038CIWM M16B M20B N24C M24B M28B Package Pin Descriptions CCLK The clock applied to this input controls the sucessive approximation conversion time interval and the acquisition time. The rise and fall times of the clock edges should not exceed 1 µs. This is the serial data clock input. The clock applied to this input controls the rate at which the serial data exchange occurs. The rising edge loads the information on the DI pin into the multiplexer address and mode select shift register. This address controls which channel of the analog input multiplexer (MUX) is selected and the mode of operation for the A/D. With CS low the falling edge of SCLK shifts the data resulting from the previous ADC conversion out on DO, with the exception of the first bit of data. When CS is low continously, the first bit of the data is clocked out on the rising edge of EOC (end of conversion). When CS is toggled the falling edge of CS always clocks out the first bit of data. CS should be brought low when SCLK is low. The rise and fall times of the clock edges should not exceed 1 µs. This is the serial data input pin. The data applied to this pin is shifted by the rising edge of SCLK into the multiplexer address and 3 DO SCLK EOC CS DI mode select register. Table 2 through Table 5 show the assignment of the multiplexer address and the mode select data. The data output pin. This pin is an active push/pull output when CS is low. When CS is high, this output is TRI-STATE. The A/D conversion result (D0–D12) and converter status data are clocked out by the falling edge of SCLK on this pin. The word length and format of this result can vary (see Table 1). The word lengt.


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