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ADC1241 Dataheets PDF



Part Number ADC1241
Manufacturers National Semiconductor
Logo National Semiconductor
Description Self-Calibrating 12-Bit Plus Sign mP-Compatible A/D Converter
Datasheet ADC1241 DatasheetADC1241 Datasheet (PDF)

ADC1241 Self-Calibrating 12-Bit Plus Sign mP-Compatible A D Converter with Sample-and-Hold November 1994 ADC1241 Self-Calibrating 12-Bit Plus Sign mP-Compatible A D Converter with Sample-and-Hold General Description The ADC1241 is a CMOS 12-bit plus sign successive approximation analog-to-digital converter On request the ADC1241 goes through a self-calibration cycle that adjusts positive linearity and full-scale errors to less than g LSB each and zero error to less than g 1 LSB The ADC1241 als.

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ADC1241 Self-Calibrating 12-Bit Plus Sign mP-Compatible A D Converter with Sample-and-Hold November 1994 ADC1241 Self-Calibrating 12-Bit Plus Sign mP-Compatible A D Converter with Sample-and-Hold General Description The ADC1241 is a CMOS 12-bit plus sign successive approximation analog-to-digital converter On request the ADC1241 goes through a self-calibration cycle that adjusts positive linearity and full-scale errors to less than g LSB each and zero error to less than g 1 LSB The ADC1241 also has the ability to go through an Auto-Zero cycle that corrects the zero error during every conversion The analog input to the ADC1241 is tracked and held by the internal circuitry and therefore does not require an external sample-and-hold A unipolar analog input voltage range (0V to a 5V) or a bipolar range ( b5V to a 5V) can be accommodated with g 5V supplies The 13-bit word on the outputs of the ADC1241 gives a 2’s complement representation of negative numbers The digital inputs and outputs are compatible with TTL or CMOS logic levels Key Specifications Y Y Y Y Y Y Resolution Conversion Time Linearity Error Zero Error Positive Full Scale Error Power Consumption g 12 Bits plus Sign 13 8ms (max) LSB ( g 0 0122%) (max) g 1LSB (max) g 1LSB (max) 70mW (max) Features Y Y Y Y Y Y Self-calibrating Internal sample-and-hold Bipolar input range with g 5V supplies and single a 5V reference No missing codes over temperature TTL MOS input output compatible Standard 28-pin DIP Applications Y Y Y Digital Signal Processing High Resolution Process Control Instrumentation TRI-STATE is a registered trademark of National Semiconductor Corporation Simplified Schematic Connection Diagram Dual-In-Line Package TL H 10554 – 2 Top View Order Number ADC1241CMJ ADC1241CMJ 883 ADC1241BIJ or ADC1241CIJ See NS Package Number J28A TL H 10554 – 1 C1995 National Semiconductor Corporation TL H 10554 RRD-B30M115 Printed in U S A Absolute Maximum Ratings (Notes 1 2) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (VCC e DVCC e AVCC) 6 5V b 6 5V Negative Supply Voltage (Vb) b 0 3V to (VCC a 0 3V) Voltage at Logic Control Inputs Voltage at Analog Input (VIN) (Vb b0 3V) to (VCC a 0 3V) AVCC-DVCC (Note 7) 0 3V g 5 mA Input Current at any Pin (Note 3) g 20 mA Package Input Current (Note 3) 875 mW Power Dissipation at 25 C (Note 4) b 65 C to a 150 C Storage Temperature Range ESD Susceptability (Note 5) 2000V Soldering Information J Package (10 sec) 300 C Operating Ratings (Notes 1 2) Temperature Range TMINsTAsTMAX b 40 C s TA s a 85 C ADC1241BIJ ADC1241CIJ ADC1241CMJ ADC1241CMJ 883 b55 CsTAs a 125 C DVCC and AVCC Voltage (Notes 6 7) 4 5V to 5 5V b 4 5V to b 5 5V Negative Supply Voltage (Vb) Reference Voltage (VREF Notes 6 7) 3 5V to AVCC a 50 mV Converter Electrical Characteristics The following specifications apply for VCC e DVCC e AVCC e a 5 0V Vb e b5 0V VREF e a 5 0V and fCLK e 2 0 MHz unless otherwise specified Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C (Notes 6 7 and 8) Symbol Parameter Conditions Typical Limit (Note 9) (Notes 10 18) Units (Limit) STATIC CHARACTERISTICS Positive Integral Linearity Error Negative Integral Linearity Error Differential Linearity Zero Error Positive Full-Scale Error Negative Full-Scale Error CREF CIN VIN VREF Input Capacitance Analog Input Capacitance Analog Input Voltage Power Supply Sensitivity Zero Error (Note 14) AVCC e DVCC e 5V g 5% e 4 75V V b e b 5V g 5% V Full-Scale Error REF Linearity Error DYNAMIC CHARACTERISTICS S (N a D) Unipolar Signal-to-Noise a Distortion Ratio (Note 17) S (N a D) Bipolar Signal-to-Noise a Distortion Ratio (Note 17) Unipolar Full Power Bandwidth (Note 17) Bipolar Full Power Bandwidth (Note 17) tAp Aperture Time Aperture Jitter 2 fIN e 1 kHz VIN e 4 85 Vp-p fIN e 10 kHz VIN e 4 85 Vp-p fIN e 1 kHz VIN e g 4 85 Vp-p fIN e 10 kHz VIN e g 4 85 Vp-p VIN e 0V to 4 85V VIN e g 4 85 Vp-p 72 72 76 76 32 25 100 100 dB dB dB dB kHz kHz ns psrms g g g ADC1241BIJ ADC1241CMJ CIJ ADC1241BIJ ADC1241CMJ CIJ After Auto-Cal (Notes 11 12) After Auto-Cal (Notes 11 12) After Auto-Cal (Notes 11 12) g g1 g1 g1 LSB(max) LSB max LSB(max) LSB(max) Bits(min) LSB(max) LSB(max) LSB(max) pF pF 12 g1 g g1 g1 g2 After Auto-Zero or Auto-Cal (Notes 12 13) After Auto-Cal (Note 12) After Auto-Cal (Note 12) 80 65 Vb b 0 05 VCC a 0 05 V(min) V(max) LSB LSB LSB Digital and DC Electrical Characteristics The following specifications apply for VCC e DVCC e AVCC e a 5 0V Vb e b5 0V VREF e a 5 0V and fCLK e 2 0 MHz unless otherwise specified Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C (Notes 6 and 7) Symbol VIN(1) VIN(0) IIN(1) IIN(0) VT a VTb VH VOUT(1) Parameter Logical ‘‘1’’ Input Voltage for All Inputs except CLK IN Logical ‘‘0’’ Input Voltage for All Inputs except CLK IN Logical ‘‘1’’ Input Current Logi.


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