HYB3117805BSJ-60

2M × 8-Bit Dynamic RAM 2k Refresh (Hyper Page Mode-EDO) Advanced Information 2 097 152 words by 8-bit organization 0 to 70 °C operating temperature Hyper Page Mode-EDO-operation Performance: -50 -60 60 15 30 104 25 HYB 5117805/BSJ-50/-60 HYB 3117805/BSJ-50/-60 tRAC tCAC tAA tRC tHPC RAS access time CAS access time Access time from address Read/Write cycle time Hyper page mode (EDO) cycle time 50 13 25 84 20 ns ns ns ns ns Power dissipation: HYB 5117805 -50 Power Supply Active TTL Standby CMOS Standby 440 11 5.5 -60 385 5 ± 10% HYB 3117805 -50 288 7.2 3.6 -60 252 mW mW mW 3.3 ± 0.3 V Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh and test mode All inputs, outputs and clocks fully TTL (5 V versions) and LV-TTL (3.3 V version)-compatible 2048 refresh cycles / 32 ms (2k-refresh) Plastic Package: P-SOJ-28-3 400 mil Semiconductor Group 1 1998-10-01 HYB 5(3)117805/BSJ-50/-60 2M × 8 EDO-DRAM The HYB 5(3)117805 are 16 MBit dynamic RAMs based on the die revisions “G” & “F” and organized as 2 097 152 words by 8-bits. The HYB 5(3)117805 utilizes a submicron CMOS silicon gate process technology, as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. Multiplexed address inputs permit the HYB 5(3)117805BJ to be packaged in a standard SOJ-28 plastic packages. Package with 400 mil width are available. These packages provide high system bit densities and are compa...