HYB314400BJ-50

1M × 4-Bit Dynamic RAM HYB 314400BJ-50/-60 Advanced Information 1 048 576 words by 4-bit organization 0 to 70 °C operating temperature Fast Page Mode Operation Performance: -50 -60 60 15 30 110 40 ns ns ns ns ns tRAC tCAC tAA tRC tPC RAS access time CAS access time Access time from address Read/Write cycle time Fast page mode cycle time 50 13 25 95 35 Fast access and cycle time Single + 3.3 V (± 0.3 V) supply with a built-in VBB generator Low power dissipation max. 252 mW active (-50 version) max. 216 mW active (-60 version) Standby power dissipation: 7.2 mW max. standby (LVTTL) 3.6 mW max. standby (LVCMOS) Output unlatched at cycle end allows two-dimensional chip selection Read, write, read-modify write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh and test mode capability All inputs and outputs LVTTL-compatible 1024 refresh cycles / 16 ms Plastic Packages: P-SOJ-26/20-2 with 300 mil width Semiconductor Group 1 1998-10-01 HYB 314400BJ-50/-60 3.3 V 1M × 4 DRAM The HYB 314400BJ is the new generation dynamic RAM organized as 1 048 576 words by 4-bit. The HYB 314400BJ utilizes CMOS silicon gate process as well as advances circuit techniques to provide wide operation margins, both internally and for the system user. Multiplexed address inputs permit the HYB 314400BJ to be packed in a standard plastic P-SOJ-26/20 package. This package size provides high system bit densities and is compatible with commonly used automatic testing and in...