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HYB3165160AT-40 Dataheets PDF



Part Number HYB3165160AT-40
Manufacturers Siemens Semiconductor Group
Logo Siemens Semiconductor Group
Description 4M x 16-Bit Dynamic RAM
Datasheet HYB3165160AT-40 DatasheetHYB3165160AT-40 Datasheet (PDF)

4M x 16-Bit Dynamic RAM ( 8k, 4k & 2k Refresh) HYB 3164160AT(L) -40/-50/-60 HYB 3165160AT(L) -40/-50/-60 HYB 3166160AT(L) -40/-50/-60 Advanced Information • • • • 4 194 304 words by 16-bit organization 0 to 70 °C operating temperature Fast Page Mode operation Performance: -40 tRAC tCAC tAA tRC tPC RAS access time CAS access time Access time from address Read/write cycle time Fast page mode cycle time 40 10 20 75 30 -50 50 13 25 90 35 -60 60 15 30 110 40 ns ns ns ns ns • • Single + 3.3 V (± .

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4M x 16-Bit Dynamic RAM ( 8k, 4k & 2k Refresh) HYB 3164160AT(L) -40/-50/-60 HYB 3165160AT(L) -40/-50/-60 HYB 3166160AT(L) -40/-50/-60 Advanced Information • • • • 4 194 304 words by 16-bit organization 0 to 70 °C operating temperature Fast Page Mode operation Performance: -40 tRAC tCAC tAA tRC tPC RAS access time CAS access time Access time from address Read/write cycle time Fast page mode cycle time 40 10 20 75 30 -50 50 13 25 90 35 -60 60 15 30 110 40 ns ns ns ns ns • • Single + 3.3 V (± 0.3V) power supply Low power dissipation: -40 HYB3166160AT(L) HYB3165160AT(L) HYB3164160AT(L) 900 756 612 -50 558 468 378 -60 396 324 270 mW mW mW • • • • • 7.2 mW standby (TTL) 3.24 mW standby (MOS) 720 µW standby for L-version Read, write, read-modify-write, CAS-before-RAS refresh (CBR), RAS-only refresh, hidden refresh and self refresh (L-version only) 2 CAS / 1 WE byte control 8192 refresh cycles /128 ms , 13 R/ 9C addresses (HYB 3164160AT) 4096 refresh cycles / 64 ms , 12 R/ 10C addresses (HYB 3165160AT) 2048 refresh cycles / 32 ms , 11 R/ 11C addresses (HYB 3166160AT) 256 msec refresh period for L-versions Plastic Package: P-TSOPII-50 400 mil Semiconductor Group 1 6.97 HYB3164(5/6)160AT(L)-40/-50/-60 4M x 16-DRAM This device is a 64 MBit dynamic RAM organized 4 194 304 by 16 bits. The device is fabricated on an advanced second generation 64Mbit 0,35µm-CMOS silicon gate process technology. The circuit and process design allow this device to achieve high performance and low power dissipation. This DRAM operates with a single 3.3 +/-0.3V power supply and interfaces with either LVTTL or LVCMOS levels. Multiplexed address inputs permit the HYB 3164(5)160AT to be packaged in a 400 mil wide TSOP-50 package. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. The HYB3164(5/6)160ATL parts (L-version) have a very low power „sleep mode“ supported by Self Refresh. Ordering Information Type 8k-refresh versions: HYB 3164160AT-40 HYB 3164160AT-50 HYB 3164160AT-60 HYB 3164160ATL-50 HYB 3164160ATL-60 4k-refresh versions: HYB 3165160AT-40 HYB 3165160AT-50 HYB 3165160AT-60 HYB 3165160ATL-50 HYB 3165160ATL-60 2k-refresh versions: HYB 3166160AT-40 HYB 3166160AT-50 HYB 3166160AT-60 HYB 3166160ATL-50 HYB 3166160ATL-60 P-TSOPII-50 P-TSOPII-50 P-TSOPII-50 P-TSOPII-50 P-TSOPII-50 400 mil 400 mil 400 mil 400 mil 400 mil DRAM (access time 40 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) P-TSOPII-50 P-TSOPII-50 P-TSOPII-50 P-TSOPII-50 P-TSOPII-50 400 mil 400 mil 400 mil 400 mil 400 mil DRAM (access time 40 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) P-TSOPII-50 P-TSOPII-50 P-TSOPII-50 P-TSOPII-50 P-TSOPII-50 400 mil 400 mil 400 mil 400 mil 400 mil DRAM (access time 40 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) Ordering Code Package Descriptions Semiconductor Group 2 HYB3164(5/6)160AT(L)-40/-50/-60 4M x 16-DRAM Pin Configuration P-TSOPII-50 (400 mil) O VCC I/O1 I/O2 I/O3 I/O4 VCC I/O5 I/O6 I/O7 I/O8 N.C. VCC WE RAS N.C. N.C. N.C. N.C. A0 A1 A2 A3 A4 A5 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 . 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS I/O16 I/O15 I/O14 I/O13 VSS I/O12 I/O11 I/O10 I/O9 N.C. VSS . LCAS UCAS OE N.C. N.C. A12/N.C. * A11/N.C.** A10 A9 A8 A7 A6 VSS * Pin 33 is A12 for HYB 3164160AT(L) and N.C. for HYB 3165(6)160AT(L) ** Pin 32 is A11 for HYB 3164(5)160AT(L) and N.C. for HYB 3166160AT(L) Pin Names A0-A12 A0-A11 A0-A10 RAS OE I/O1-I/O16 UCAS,LCAS WE Vcc Vss Address Inputs for 8k-refresh version HYB 3164160AT(L) Address Inputs for 4k-refresh version HYB 3165160AT(L) Address Inputs for 2k-refresh version HYB 3166160AT(L) Row Address Strobe Output Enable Data Input/Output Column Address Strobe Read/Write Input Power Supply ( + 3.3V) Ground Semiconductor Group 3 HYB3164(5/6)160AT(L)-40/-50/-60 4M x 16-DRAM TRUTH TABLE FUNCTION Standby Read:Word Read:Lower Byte Read:Upper Byte Write:Word (Early-Write) Write:Lower Byte (Early-Write) Write:Upper Byte (Early Write) Read-ModifyWrite Fast Page Mode Read (Word) Fast Page Mode Read (Word) 1st Cycle 2nd Cycle RAS H L L L L L L L L L L L L L L H-L H-L L-HL L-HL LCAS H-X L L H L L H L H-L H-L H-L H-L H-L H-L H L L L L UCAS H-X H H L L H L L H-L H-L H-L H-L H-L H-L H L L L L WE X H H H L L L H-L H H L L H-L H-L X H L H L OE X L L L X X X L-H L L X X L-H L-H X X X L X ROW ADD X ROW ROW ROW ROW ROW ROW ROW ROW n/a ROW n/a ROW n/a ROW X X ROW ROW COL ADD X COL COL COL COL COL COL COL COL COL COL COL COL COL n/a n/a n/a COL COL I/O1I/O16 High Impedance Data Out Lower Byte:Data Out Upper-Byte:High-Z Lower Byte:High-Z Upper Byte:Data Out Data In Lower Byte:Data Out Upper-Byte:High-Z Lower Byte:High-Z Upper Byte:Data Out Data Out, Data In Data Out Data Out .


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