Document
8M x 8-Bit Dynamic RAM (4k & 8k Refresh, EDO-version)
HYB 3164805J/T(L) -50/-60 HYB 3165805J/T(L) -50/-60
Preliminary Information
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8 388 608 words by 8-bit organization 0 to 70 ˚C operating temperature Fast access and cycle time RAS access time: 50 ns (-50 version) 60 ns (-60 version) Cycle time: 84 ns (-50 version) 104 ns (-60 version) CAS access time: 13 ns ( -50 version) 15 ns ( -60 version) Hyper page mode (EDO) cycle time 20 ns (-50 version) 25 ns (-60 version) Single + 3.3 V (± 0.3V) power supply Low power dissipation max. 396 active mW ( HYB 3164805J/T(L)-50) max. 360 active mW ( HYB 3164805J/T(L)-60) max. 504 active mW ( HYB 3165805J/T(L)-50) max. 432 active mW ( HYB 3165805J/T(L)-60) 7.2 mW standby (TTL) 720 W standby (MOS) 14.4 mW Self Refresh (L-version only) Read, write, read-modify-write, CAS-before-RAS refresh (CBR), RAS-only refresh, hidden refresh and self refresh modes Hyper page mode (EDO) capability 8192 refresh cycles/128 ms , 13 R/ 11C addresses (HYB 3164805J/T(L)) 4096 refresh cycles/ 64 ms , 12 R/ 12C addresses (HYB 3165805J/T(L)) Plastic Package: P-SOJ-34-1 500 mil HYB 3164(5)805J P-TSOPII-34-1 500 mil HYB 3164(5)805T(L)
Semiconductor Group
149
HYB3164(5)805J/T(L)-50/-60 8M x 8 EDO-DRAM
This HYB3164(5)805 is a 64 MBit dynamic RAM organized 8 388 608 x 8 bits. The device is fabricated in SIEMENS/IBM most advanced first generation 64Mbit CMOS silicon gate process technology. The circuit and process design allow this device to achieve high performance and low power dissipation. The HYB3164(5)805 operates with a single 3.3 +/-0.3V power supply and interfaces with either LVTTL or LVCMOS levels. Multiplexed address inputs permit the HYB 3164(5)805 to be packaged in a 500mil wide SOJ-34 or TSOP-34 plastic package. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment.The HYB3164(5)805TL parts have a very low power „sleep mode“ supported by Self Refresh. Ordering Information Type HYB 3164805J-50 HYB 3164805J-60 HYB 3164805T-50 HYB 3164805T-60 Ordering Code on request on request on request on request Package P-SOJ-34-1 P-SOJ-34-1 P-TSOPII-34-1 P-TSOPII-34-1 P-TSOPII-34-1 P-TSOPII-34-1 P-SOJ-34-1 P-SOJ-34-1 P-TSOPII-34-1 P-TSOPII-34-1 P-TSOPII-34-1 P-TSOPII-34-1 Descriptions 500 mil DRAM (access time 50 ns) 500 mil DRAM (access time 60 ns) 500 mil DRAM (access time 50 ns) 500 mil DRAM (access time 60 ns) 500 mil DRAM (access time 50 ns) 500 mil DRAM (access time 60 ns) 500 mil DRAM (access time 50 ns) 500 mil DRAM (access time 60 ns) 500 mil DRAM (access time 50 ns) 500 mil DRAM (access time 60 ns) 500 mil DRAM (access time 50 ns) 500 mil DRAM (access time 60 ns)
HYB 3164805TL-50 on request HYB 3164805TL-60 on request HYB 3165805J-50 HYB 3165805J-60 HYB 3165805T-50 HYB 3165805T-60 on request on request on request on request
HYB 3165805TL-50 on request HYB 3165805TL-60 on request Pin Names A0-A12 A0-A11 RAS OE I/O1-I/O8 CAS WRITE Vcc Vss
Address Inputs for HYB 3164805J/T(L) Address Inputs for HYB 3165805J/T(L) Row Address Strobe Output Enable Data Input/Output Column Address Strobe Read/Write Input Power Supply ( + 3.3V) Ground
Semiconductor Group
150
HYB3164(5)805J/T(L)-50/-60 8M x 8 EDO-DRAM
P-SOJ-34-1 (500 mil) P-TSOPII-34-1 (500 mil)
Pin Configuration
Semiconductor Group
151
HYB3164(5)805J/T(L)-50/-60 8M x 8 EDO-DRAM
TRUTH TABLE
FUNCTION Standby Read Early-Write Delayed-Write Read-Modify-Write Hyper Page Mode Read 1st Cycle 2nd Cycle Hyper Page Mode Write 1st Cycle 2nd Cycle Hyper Page Mode RMW 1st Cycle 2st Cycle RAS only refresh CAS-before-RAS refresh Test Mode Entry Hidden Refresh READ WRITE Self Refresh (L-version only)
RAS H L L L L L L L L L L L H-L H-L L-H-L L-H-L H-L
CAS H-X L L L L H-L H-L H-L H-L H-L H-L H L L L L L
WRITE X H L H-L H-L H H L L H-L H-L X H L H L H
OE X L X H L-H L L X X L-H L-H X X X L X X
ROW ADDR X ROW ROW ROW ROW ROW n/a ROW n/a ROW n/a ROW X X ROW ROW X
COL ADDR X COL COL COL COL COL COL COL COL COL COL n/a n/a n/a COL COL X
I/O1I/O4 High Impedance Data Out Data In Data In Data Out, Data In Data Out Data Out Data In Data In Data Out, Data In Data Out, Data In High Impedance High Impedance High Impedance Data Out Data In High Impedance
Semiconductor Group
152
HYB3164(5)805J/T(L)-50/-60 8M x 8 EDO-DRAM
Block Diagram for HYB 3165805J/T(L)
Semiconductor Group
153
HYB3164(5)805J/T(L)-50/-60 8M x 8 EDO-DRAM
Block Diagram for HYB 3164805J/T(L)
Semiconductor Group
154
HYB3164(5)805J/T(L)-50/-60 8M x 8 EDO-DRAM
Absolute Maximum Ratings Operating temperature range..............................................................................................0 to 70 ˚C Storage temperature range.........................................................................................– 55 to 150 ˚C Input/output voltage..................................................................................-0.5 to min (Vcc+0.5,4.6) V Power supply vo.