HT6576

HT6576A Advanced SCSI CHIP Features Support the ANSI X3.131-1986 standard Asynchronous transfer rate to 5 Mbyte/sec Support initiator and target mode 0.8um CMOS process On chip 48mA single-ended drivers and receivers Non internal clock needed 44pins PLCC package Block Diagram 1 14th July ’97 HT6576A Pin Diagram Pin Description Host Interface Signal Pin No 14~16 17 11 9 24~28, 20~22 10 19 18 8 13 7 Pin Name A0~A2 CS DACK DRQ D0~D7 EOP IOR IOW IRQ READY RESET I/O I I I O I/O I I I O O I Address Lines Chip Select, active low Description DMA Acknowledge, active low DMA Request Data Lines End of Process, active low I/O Read, active low I/O Write, active low Interrupt Request Ready Reset, active low 2 14th July ’97 HT6576A SCSI Interface Signals Pin No 33 6 4 30 32 29 34 2 37~41, 43, 44, 1 35 5 VSS Pin Name ACK ATN BSY C/D I/O MSG REQ RST DB0–DB7 DBP SEL I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Description Acknowledge, active low Attention, active low Busy, active low Control/Data, active low Input/Output, active low Message, active low Request, active low Reset, active low SCSI Data Bus, active low SCSI Parity Bit, active low Select, active low 3, 12, 31, 36, 42 VDD 23 Registers Address 0 Current SCSI data register(READ ONLY) DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 The SCSI bus parity is checked at the beginning of the read cycle. Output data register(WRITE ONLY) DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 3 14th July ’97 HT6576A Address 1: Initiator c...