Ring Generator. HV450 Datasheet

HV450 Generator. Datasheet pdf. Equivalent

Part HV450
Description High-Voltage Ring Generator
Feature HV450 High-Voltage Ring Generator Ordering Information Operating Voltage VNN1 -220V Package Options.
Manufacture Supertex Inc
Datasheet
Download HV450 Datasheet



HV450
HV450
High-Voltage Ring Generator
Ordering Information
Operating Voltage
VNN1
-220V
Package Options
SOW-16
HV450WG
Features
Integrated high voltage transistors
67VRMS ring signal
Output over current protection
Can drive external MOSFETs for larger loads
Applications
High voltage ring generator
Set-top/Street box ring generator
Pair gain ring generator
General Description
The Supertex HV450 is a PWM high voltage ring generator. The
high voltage output P- and N-channel transistors are controlled
independently by the logic inputs PIN and NIN. For application
where a single control pin (NIN) is desired, the mode pin should
be connected to Gnd. This adds a 200ns deadband on the
control logic to avoid cross conduction on the high voltage
output. A logic high on NIN will turn the high voltage P-Channel on
and the N-Channel off. The outputs can drive up to 5 RENs. The
HV450 can drive external MOSFETs for applications requiring
larger loads. The IC can be powered down by connecting the
enable pin to VDD. The high voltage outputs have pulse by pulse
over current protection.
Pin Configuration
Absolute Maximum Ratings*
VNN1, power supply voltage
VPP, P-channel gate voltage supply
VNN2, N-channel gate voltage supply
VDD, logic supply
Storage temperature
Power dissipation
-240V
-20V
VNN1+20V
+7.5V
-65°C to +150°C
600mW
* All voltages referenced to ground
N/C
PGND
GND
Mode
PIN
NIN
EN
VDD
1
2
3
4
5
6
7
8
top view
SOW-16
16 VPP
15 PGATE
14 VPSEN
13 HVOUT
12 VNSEN
11 NGATE
10 VNN2
9 VNN1
12/13/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and s1pecifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.



HV450
Electrical Characteristics
(Over operating supply voltages unless otherwise specified, TA = -40°C to +85°C.)
Symbol Parameters
Min Typ
Max
Unit
VPP
VNN1
VNN2
VDD
INN1Q
P-channel linear regulator output voltage
-10
-18
High voltage negative supply
- 220
-110
Negative linear regulator output voltage VNN1 + 6.0
Logic supply voltage
4.5
VNN1 + 10.0
5.5
VNN1 quiescent current
300 500
25
V
V
V
V
µA
IDDQ
VDD1 quiescent current
90 200
35 100 µA
INN1 VNN1 operating current
1.4 mA
IDD VDD operating current
IIL Mode logic input low current
VIL Logic input low voltage
VIH Logic input high voltage
1.0 mA
25 µA
0 1.0 V
4.0 5.0 V
HV450
Conditions
PIN = NIN = EN = L
PIN = NIN = L, EN = H
PIN = NIN = EN = L
PIN = NIN = L, EN = H
No load, VOUTP and VOUTN switching at
100KHz
Mode = 0V
VDD = 5.0V
VDD = 5.0V
High Voltage Output
Symbol Parameters
Min Typ Max Unit Conditions
RSOURCE VOUTP source resistance
RSINK VOUTP sink resistance
td(ON)
HVOUT delay time
trise HVOUT rise time
td(OFF) HVOUT delay time
tfall HVOUT fall time
tdb Logic deadband time
Vpsen HVOUT current source sense voltage
Vnsen HVOUT current sink sense voltage
tshortP
HVOUT off delay time when current
source sense is activiated
65 IOUT = 100mA
65 IOUT = -100mA
150 ns PIN = high to low, Mode = high
50 ns PIN = high to low
200 ns NIN = low to high, Mode = high
50 ns NIN = low to high
250 ns Mode = low
-1.2 -0.8 V
VNN1 + 0.8
VNN1 + 1.2 V
70 150 ns
tshortN
HVOUT off delay time when current sink
sense is activated
70 150 ns
twhout
twlout
Minimum pulse width for HVOUT at PGND
Minimum pulse width for HVOUT at VNN1
500 ns
500 ns
Truth Table
NIN PIN Mode
LL
H
LH H
H* L*
H
HH
H
LX
L
HX
L
XX
X
*This state will short VNN1 to Pgnd and should therefore be avoided.
EN
L
L
L
L
L
L
H
HVOUT
Pgnd
High Z
*
VNN1
VNN1
Pgnd
High Z
2







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