Parallel Converter. HV57708 Datasheet

HV57708 Converter. Datasheet pdf. Equivalent

Part HV57708
Description 64-Channel Serial to Parallel Converter
Feature Supertex inc. HV57708 32MHz, 64-Channel Serial to Parallel Converter with Push-Pull Outputs Featu.
Manufacture Supertex Inc
Datasheet
Download HV57708 Datasheet



HV57708
Supertex inc.
HV57708
32MHz, 64-Channel Serial to Parallel Converter
with Push-Pull Outputs
Features
►HVCMOS® technology
►5.0V CMS Logic
►Output voltage up to +80V
►Low power level shifting
►32MHz equivalent data rate
►Latched data outputs
►Foreward and reverse shifting options (DIR pin)
Diode to VPP allows efficient power recovery
►Outputs may be hot switched
General Description
The HV57708 is a low voltage serial to high voltage parallel
converter with push-pull outputs. The device has been
designed for use as a driver for EL displays. It can also be
used in any application requiring multiple output high voltage
current sourcing and sinking capability such as driving
plasma panels, vacuum fluorescent displays, or large matrix
LCD displays.
The device has 4 parallel 16-bit registers, permitting data
rates 4x the speed of one (they are clocked together). There
are also 64 latches and control logic to perform the polarity
select and blanking of the outputs. HVOUT1 is connected to
the first stage of the first shift register through the polarity
and blanking logic. Data is shifted through the shift registers
on the logic low to high transition of the clock. The DIR pin
causes CCW shifting when connected to GND, and CW
shifting when connected to VDD. A data output buffer is
provided for cascading devices. This output reflects the
current status of the last bit of the shift register (HVOUT64).
Operation of the shift register is not affected by the LE (latch
enable), BL (blanking), or the POL (polarity) inputs. Transfer
of data from the shift registers to the latches occurs when
the LE input is high. The data in the latches is stored when
the LE is low.
Functional Block Diagram
DO1 DO2
DI4 DI3
DO3
DI2
DO4
DI1
VDD
LE
BL
POL
VPP
DIR
SR1
HVOUT15
9
HVOUT61
CLK
SR2
SR3
HVOUT26
10
HVOUT62
HVOUT37
11
HVOUT63
SR4
HVOUT48
12
HVOUT64
Doc.# DSFP-HV57708
A061913
DO4 DO3 DO2 DO1
GND
Note:
DI1 DI2 DI3 DI4
Each SR (shift register) provides 16 outputs. SR1 supplies every fourth output starting with 1;
SR2 supplies every fourth output with 2, etc.
Supertex inc.
www.supertex.com



HV57708
Ordering Information
Part Number
Package Option
HV57708PG-G
80-Lead PQFP
-G denotes a lead (Pb)-free / RoHS compliant package
Packing
66/Tray
Pin Configuration
HV57708
Absolute Maximum Ratings
Parameter
Value
Supply voltage, VDD
Output voltage , VPP
Logic input levels
Ground current1
Continuous total power dissipation2
-0.5V to +7.5V
-0.5V to +90V
-0.3V to VDD +0.3V
1.5A
1200mW
Operating temperature range
-40°C to +85°C
Storage temperature range
-65°C to +150°C
Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect
device reliability. All voltages are referenced to device ground.
Notes:
1. Limited by the total power dissipated in the package.
2. For operation above 25°C ambient derate linearly to maximum
operating temperature at 20mW/°C.
80
1
80-Lead PQFP
Product Marking
HV57708PG
LLLLLLLLLL
YYWW
CCCCCCCC AAA
L = Lot Number
YY = Year Sealed
WW = Week Sealed
C = Country of Origin
A = Assembler ID
= “Green” Packaging
Package may or may not include the following marks: Si or
80-Lead PQFP
Typical Thermal Resistance
Package
θja
80-Lead PQFP
37OC/W
Recommended Operating Conditions
Sym
Parameter
VDD Logic supply voltage
VPP Output voltage
VIH High-level input voltage
VIL Low-level input voltage
fCLK Clock frequency per register
TA Operating free-air temperature
Notes:
Power-up sequence should be the following:
1. Apply ground.
2. Apply VDD.
3. Set all inputs (DIN, CLK, Enable, etc.) to a known state.
4. Apply VPP.
5. The VPP should not drop below VDD or float during operation.
Power-down sequence should be the reverse of the above.
Min
4.5
8.0
VDD -0.5V
0
-
-40
Max
5.5
80
-
0.5
8.0
+85
Units
V
V
V
V
MHz
°C
Doc.# DSFP-HV57708
A061913
Supertex inc.
2 www.supertex.com







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