Column Driver. HV623 Datasheet

HV623 Driver. Datasheet pdf. Equivalent

Part HV623
Description 32-Channel 128-Level Amplitude Gray-Shade Display Column Driver
Feature HV623 32-Channel 128-Level Amplitude Gray-Shade Display Column Driver Ordering Information Package O.
Manufacture Supertex Inc
Datasheet
Download HV623 Datasheet




HV623
HV623
32-Channel 128-Level Amplitude Gray-Shade
Display Column Driver
Ordering Information
Device
HV623
Package Option
64-Lead 3-sided Plastic Gullwing
HV623PG
Features
5V CMOS inputs
Up to 80V modulation voltage
Capable of 128 levels of gray shading
20MHz data throughput rate
32 outputs per device (can be cascaded)
Pin-programmable shift direction (DIR)
D/A conversion cycle time is 32µs
Diodes in output structure allow usage
in energy recovery systems
Integrated HVCMOS® technology
Available in 3-sided 64-lead gullwing package
Absolute Maximum Ratings
Supply voltage, VDD1
Supply voltage, VPP1
Logic input levels1
Ground current 2
Continuous total power dissipation3
-0.5V to +7.5V
-0.5V to +90V
-0.5 to VDD + 0.5V
1.5A
1W
Operating temperature range
Storage temperature range
Lead temperature 1.6mm (1/16 inch)
from case for 10 seconds
-40°C to +70°C
-65°C to +150°C
260°C
Notes:
1. All voltages are referenced to GND.
2. Duty cycle is limited by the total power dissipated in the package.
3. For operation above 25°C ambient derate linearly to 70°C at 22.2mW/°C.
General Description
The HV623 is a 32-channel driver IC for gray shade display use.
It is designed to produce varying output voltages between 3 and
80 volts. This amplitude modulation at the output is facilitated by
an external ramp voltage VR. See Theory of Operation for detailed
explanation.
This device consists of a dual 16-bit shift registers, 32 data latches
and comparators, and control logic to preform 128 levels of gray
shading. There are 7 bits of data inputs. Data is shifted through the
shift registers at both edges of the clock, resulting a data transfer
rate of twice of the shift clock frequency. When the DIR pin is high,
CSI/CSO is the input/output for the chip select pulse. When DIR
is low, CSI/CSO is the output/input for the chip select pulse. The
DIR = HIGH also allows the HV623 to shift data in the counter-
clockwise direction when viewed from the top of the package.
When the DIR pin is low, data is shifted in the clockwise direction.
The output circuitry allows the energy which is stored in the output
capacitance to be returned to VPP through the body diode of the
output transistor.
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HV623
HV623
Electrical Characteristics (at TA = 25°C, over operating conditions unless otherwise specified)
Low-Voltage DC Characteristics (Digital)
Symbol
Parameter
Min Typ1 Max Units
Conditions
IDD VDD supply current
IDDQ Quiescent VDD supply current
IIH High-level input current
IIL Low-level input current
CIN2 Input capacitance (data, LC, SC, CC)
IOH High-level output current
IOL Low-level output current
Notes
1. All typical values are at VDD = 5.0V.
2. Guaranteed by design.
12 20 mA fSC = 10MHz
fCC = 8MHz
100 µA All VIN = 0V, VDD = max
1.0 50 µA VIH = VDD
-1.0 -50 µA VIL = 0V
15 pF VIN = 0V, f = 1MHz
-2 mA VDD = 4.5V
2 mA VDD = 4.5V
Low-Voltage DC Characteristics (Analog)
Symbol
Parameter
IDD VDD supply current
IDDQ Quiescent VDD supply current
Min Typ Max Units
Conditions
100 µA fSC =10MHz
fCC = 8MHz
100 µA All VIN = 0V, VDD = max
High-Voltage Bias Circuit for Output Variation Control
Symbol
Parameter
Min Typ Max Units
Conditions
IPP VPP supply current for bias circuit
2 mA Depending on external
bias circuit, see Table 1.
High-Voltage DC Characteristics
Symbol
Parameter
IAOH High-voltage analog output source current
Min Typ Max Units
See Performance Curves mA
IAOL High-voltage analog output sink current
See Performance Curves mA
VO Maximum delta voltage between high voltage outputs
of the same level
±0.2 V
Conditions
VPP = 80V
See test circuit
VPP = 80V, VDD = 4.5V
VAO = 2V
At all gray levels
Recommended Operating Conditions
Symbol
Parameter
VDD
VDD
VIH
VIL
VBIAS
VCTL
VPP
VR
fSC
TA
Low-voltage digital supply voltage
Low-voltage analog supply voltage
High-level input voltage (analog and digital)
Low-level input voltage (analog and digital)
IPP control circuit bias voltage
IPP control circuit control voltage
High-voltage supply
Ramp voltage
Shift clock operating frequency (at VDD = 5.5V)
Operating free-air temperature
Notes:
Power-up sequence should be the following:
1. Connect ground. 2. Apply VDD. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state.
Power-down sequence should be the reverse of the above.
Min
4.5
4.5
VDD -1
0
-2
-0.3
0
-40
4. Apply VPP.
Typ
5.0
5.0
0
0
Max
5.5
5.5
VDD
1
2
80
VPP -2
10.2
70
Units
V
V
V
V
V
V
V
V
MHz
°C
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