Row Driver. HV7224 Datasheet

HV7224 Driver. Datasheet pdf. Equivalent

Part HV7224
Description 40-Channel Symmetric Row Driver
Feature Supertex inc. HV7224 40-Channel Symmetric Row Driver Features ►►HVCMOS® technology ►►Symmetric ro.
Manufacture Supertex Inc
Datasheet
Download HV7224 Datasheet




HV7224
Supertex inc.
HV7224
40-Channel
Symmetric Row Driver
Features
►HVCMOS® technology
►Symmetric row drive (reduces latent imaging in
ACTFEL displays)
►Output voltage up to +240V
►Low power level shifting
►Source/sink current minimum 70mA
►Shift register speed 3.0MHz
►Pin-programmable shift direction (DIR, SHIFT)
General Description
The HV7224 is a low-voltage serial to high-voltage parallel
converter with push-pull outputs. It is especially suitable for use
as a symmetric row driver in AC thin-film electroluminescent
(ACTFEL) displays.
When the data reset pin (DRIOA/DRIOB) is at logic high, it will reset
all the outputs of the internal shift register to zero. At the same
time, the output of the shift register will start shifting a logic high
from the least significant bit to the most significant bit. The DRIOA/
DRIOB can be triggered at any time. The DIR and SHIFT pins
control the direction of data shift through the device. When DIR is
at logic high, DRIOA is the input and DRIOB is the output. When DIR
is grounded, DRIOB is the input and the DRIOA is the output. See
the Output Sequence Operation Table for output sequence. The
POL and OE pins perform the polarity select and output enable
function respectively. Data is loaded on the low to high transition
of the clock. A logic high will cause the output to swing to VPP if
POL is high, or to GND if POL is low. All outputs will be in High-Z
state if OE is at logic high. Data output buffers are provided for
cascading devices.
Functional Block Diagram
VPP
OE
POL
VDD
DRIOA
Level
Translator
P
HVOUT1
N
SHIFT
CLK
DIR
S/R
Level
Translator
P
HVOUT2
N
Doc.# DSFP-HV7224
C072413
DRIOB
GND
Level
Translator
P
HVOUT40
N
Supertex inc.
www.supertex.com



HV7224
Ordering Information
Part Number
Package
HV7224PG-G
64-Lead PQFP
-G denotes a lead (Pb)-free / RoHS compliant package
Packing
66/Tray
Absolute Maximum Ratings
Parameter
Value
Supply voltage, VDD
Supply voltage , VPP
Logic input levels
Continuous total power dissipation1
-0.5V to +7.0V
-0.5V to +260V
-0.5V to VDD + 0.5V
1200mW
Operating temperature range
-40°C to +85°C
Storage temperature range
-65°C to +150°C
Absolute Maximum Ratings are those values beyond which damage to
the device may occur. Functional operation under these conditions is not
implied. Continuous operation of the device at the absolute rating level
may affect device reliability. All voltages are referenced to device ground.
Note:
1. For operation above 25°C ambient derate linearly to maximum
operating temperature at 20mW/°C.
Pin Configuration
64
HV7224
1
64-Lead PQFP (3-sided)
(top view)
Product Marking
Top Marking
HV7224PG
LLLLLLLLLL
YYWW
CCCCCCCC AAA
L = Lot Number
YY = Year Sealed
WW = Week Sealed
C = Country of Origin
A = Assembler ID
= “Green” Packaging
Package may or may not include the following marks: Si or
64-Lead PQFP (3-sided)
Typical Thermal Resistance
Package
θja
44-Lead PLCC
37OC/W
Recommended Operating Conditions
Sym
Parameter
VDD Logic supply voltage
VPP High voltage supply1
VIH High-level input voltage
VIL Low-level input voltage
fCLK Clock frequency
TA Operating free-air temperature
IO High voltage output current
IOD Allowable pulsed current through output diode
Note:
1. Output will not switch at VPP = 0V.
Power-up sequence should be the following:
1. Connect ground.
2.
3.
ASpept layllVinDpD.uts (Data, CLK, Enable, etc.) to a known state.
4.
The
VAPpPpslhyoVuPlPd.
not
drop
below
VDD
or
float
during
operation.
Power-down sequence should be the reverse of the above.
Min
4.5
0
0.7 VDD
0
-
-40
-
-
Max
5.5
240
VDD
0.2VDD
3.0
+85
±70
±300
Units
V
V
V
V
MHz
°C
mA
mA
Doc.# DSFP-HV7224
C072413
Supertex inc.
2 www.supertex.com







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