Push-Pull Outputs. HV9708 Datasheet

HV9708 Outputs. Datasheet pdf. Equivalent

Part HV9708
Description 32-Channel Serial To Parallel Converter With High Voltage Push-Pull Outputs
Feature HV9708 HV9808 32-Channel Serial To Parallel Converter With High Voltage Push-Pull Outputs Ordering I.
Manufacture Supertex Inc
Datasheet
Download HV9708 Datasheet




HV9708
HV9708
HV9808
32-Channel Serial To Parallel Converter
With High Voltage Push-Pull Outputs
Ordering Information
Package Options
Device
44 J-Lead Quad
Plastic Chip Carrier
Die
in waffle pack
HV9708
HV9808
HV9708PJ
HV9808PJ
HV9708X
HV9808X
Features
Processed with HVCMOS® technology
Output voltages up to 80V
Low power level shifting
Shift register speed 8MHz
Latched data outputs
Forward and reverse shifting options
Diode to VPP allows efficient power recovery
5V CMOS compatible inputs
Absolute Maximum Ratings1
Supply voltage, VDD2
Output voltage, VPP2
Logic input levels2
Ground current3
-0.5V to +7V
VDD to +90V
-0.5V to VDD +0.5V
1.5A
Continuous total power dissipation4
1200mW
Operating temperature range
-40°C to +85°C
Storage temperature range
-65°C to +150°C
Lead temperature 1.6mm (1/16 inch)
from case for 10 seconds
260°C
Notes:
1. Device will survive (but operation may not be specified or guaranteed) at
these extremes.
2. All voltages are referenced to GND.
3. Duty cycle is limited by the total power dissipated in the package.
4. For operation above 25°C ambient, derate linearly to 70°C at 12mW/°C.
General Description
The HV97 and HV98 are low-voltage serial to high-voltage paral-
lel converters with push-pull outputs. These devices have been
designed for use as drivers for AC-electroluminescent displays.
They can also be used in any application requiring multiple output
high-voltage current sourcing and sinking capabilities such as
driving plasma panels, vacuum fluorescent displays, or large
matrix LCD displays. The inputs are fully CMOS compatible.
These devices consist of a 32-bit shift register, 32 latches, and
control logic to perform the polarity select and blanking of the
outputs. HVOUT1 is connected to the first stage of the shift register
through the polarity and blanking logic. Data is shifted through the
shift register on the logic low to high transition of the clock. The
HV97 shifts data in the clockwise direction when viewed from the
top of the package and the HV98 shifts in the counterclockwise
direction. A data output buffer is provided for cascading devices.
This output reflects the current status of the last bit of the shift
register (HVOUT32). Operation of the shift register is not affected
by the LE (latch enable), BL (blanking), or the POL (polarity) in-
puts. Transfer of data from the shift register to the latch occurs
when the LE (latch enable) input is high. The data in the latch is
stored when LE is low.
02/96/022
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex prod1ucts, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.



HV9708
Electrical Characteristics (VPP = 60V, VDD = 5V, TA =25°C)
DC Characteristics
Symbol
Parameter
Min Max
IPP VPP Supply Current
IDDQ IDD Supply Current (Quiescent)
IDD IDD Supply Current (Operating)
100
100
15
VOH (Data)
VOL (Data)
IIH
IIL
VOC
VOH
VOL
Shift Register Output Voltage
Shift Register Output Voltage
Current Leakage, any input
Current Leakage, any input
HVOUT Output Clamp Diode Voltage
HVOUT Output when Sourcing
HVOUT Output when Sinking
VDD-0.5
52
0.5
1
-1
-1.5
4
AC Characteristics
Symbol
Parameter
fCLK
tWL or tWH
tSU
tH
tDLH (Data)
tDHL (Data)
tDLE
tWLE
tSLE
tON
tOFF
Clock Frequency
Clock width, HIGH or LOW
Setup time before CLK rises
Hold time after CLK rises
Data Output Delay after L to H CLK
Data Output Delay after H to L CLK
LE Delay after L to H CLK
Width of LE Pulse
LE Setup Time before L to H CLK
Delay from LE to HVOUT, L to H
Delay from LE to HVOUT, H to L
Min Max
8
62
25
10
110
110
50
50
50
500
500
Recommended Operating Conditions
Symbol
Parameter
VDD Logic Voltage Supply
VPP High Voltage Supply
VIH Input HIGH Voltage
VIL Input LOW Voltage
fCLK Clock Frequency
TA Operating free-air temperature
Notes:
Power-up sequence should be the following:
1. Connect ground.
2. Apply VDD.
3. Set all inputs (Data, CLK, Enable, etc.) to a known state.
4. Apply VPP.
Power-down sequence should be the reverse of the above.
5. The VPP should not drop below VDD or float during operations.
Min
4.5
8.0
VDD-0.5
0
0
-40
Max
5.5
80
VDD
0.5
8
+85
Units
µA
µA
mA
V
V
µA
µA
V
V
V
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
V
V
V
V
MHz
°C
HV9708/HV9808
Conditions
HVOUT outputs HIGH to LOW
All inputs = VDD or GND
VDD = VDD max,
fCLK = 8 MHz
IO = -100µA
IO = 100µA
Input = VDD
Input = GND
IOC = -5mA
IOH = -20mA, 0 to 70°C
IOL = 5mA, 0 to 70°C
Conditions
CL = 15pF
CL = 15pF
Comments
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