Line Receiver. HS-26C32RH Datasheet

HS-26C32RH Receiver. Datasheet pdf. Equivalent

Part HS-26C32RH
Description Radiation Hardened Quad Differential Line Receiver
Feature Radiation Hardened Quad Differential Line Receiver HS-26C32RH, HS-26C32EH The Intersil HS-26C32RH, .
Manufacture Intersil Corporation
Datasheet
Download HS-26C32RH Datasheet



HS-26C32RH
Radiation Hardened Quad Differential Line Receiver
HS-26C32RH, HS-26C32EH
The Intersil HS-26C32RH, HS-26C32EH are differential line
receivers designed for digital data transmission over balanced
lines and meets the requirements of EIA Standard RS-422.
Radiation hardened CMOS processing assures low power
consumption, high speed, and reliable operation in the most
severe radiation environments.
The HS-26C32RH, HS-26C32EH have an input sensitivity
typically of 200mV over the common mode input voltage
range of 7V. The receivers are also equipped with input fail
safe circuitry, which causes the outputs to go to a logic “1”
when the inputs are open. Enable and Disable functions are
common to all four receivers.
Specifications for Rad Hard QML devices are controlled by the
Defense Logistics Agency Land and Maritime (DLA). The SMD
numbers listed in the “Ordering Information” table must be
used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95689.
Features
• Electrically screened to SMD #5962-95689
• QML qualified per MIL-PRF-38535 requirements
• 1.2 micron radiation hardened CMOS
- Total dose . . . . . . . . . . . . . . . . . . . . . . . . 300 krad(Si) (max)
• Latch-up free
• EIA RS-422 compatible inputs
• CMOS compatible outputs
• Input fail safe circuitry
• High impedance inputs when disabled or powered down
• Low power dissipation 138mW standby (max)
• Single 5V supply
• Full -55°C to +125°C military temperature range
Applications
• Line receiver for MIL-STD-1553 serial data bus
Ordering Information
ORDERING NUMBER
(Note 1)
INTERNAL
MKT. NUMBER
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
5962F9568901QEC
HS1-26C32RH-8
Q 5962F95 68901QEC
-55 to +125 16 Ld SBDIP
D16.3
5962F9568901QXC
HS9-26C32RH-8
Q 5962F95 68901QXC
-55 to +125 16 Ld FLATPACK K16.A
5962F9568901V9A
HS0-26C32RH-Q
-55 to +125 Die
HS0-26C32RH/SAMPLE HS0-26C32RH/SAMPLE
-55 to +125 Die
5962F9568901VEC
HS1-26C32RH-Q
Q 5962F95 68901VEC
-55 to +125 16 Ld SBDIP
D16.3
5962F9568901VXC
HS9-26C32RH-Q
Q 5962F95 68901VXC
-55 to +125 16 Ld FLATPACK K16.A
HS1-26C32RH/PROTO HS1-26C32RH/PROTO
HS1- 26C32RH /PROTO
-55 to +125 16 Ld SBDIP
D16.3
HS9-26C32RH/PROTO HS9-26C32RH/PROTO
HS9- 26C32RH /PROTO
-55 to +125 16 Ld FLATPACK K16.A
5962F9568903VEC
HS1-26C32EH-Q
Q 5962F95 68903VEC
-55 to +125 16 Ld SBDIP
D16.3
5962F9568903VXC
HS9-26C32EH-Q
Q 5962F95 68903VXC
-55 to +125 16 Ld FLATPACK K16.A
5962F9568903V9A
HS0-26C32EH-Q
Q 5962F95 68903V9A
-55 to +125 Die
5962F9568901VYC
HS9G-26C32RH-Q (Note 2)
Q 5962F95 68901VYC
-55 to +125 16 Ld FLATPACK K16.A
HS9G-26C32RH/PROTO HS9G-26C32RH/PROTO (Note 2) HS9G-26C32RH/PROTO
-55 to +125 16 Ld FLATPACK K16.A
NOTES:
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
2. The lid of these packages are connected to the ground pin of the device.
May 28, 2013
FN3402.5
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2012, 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.



HS-26C32RH
Logic Diagram
HS-26C32RH, HS-26C32EH
ENABLE ENABLE DIN DIN
CIN CIN
BIN BIN AIN AIN
+-
+-
+-
+-
DOUT
COUT
BOUT
AOUT
Pin Configurations
HS1-26C32RH, HS1-26C32EH
(16 LD SBDIP)
MIL-STD-1835: CDIP2-T16
TOP VIEW
AIN 1
AIN 2
AOUT 3
ENABLE 4
COUT 5
CIN 6
CIN 7
GND 8
16 VDD
15 BIN
14 BIN
13 BOUT
12 ENABLE
11 DOUT
10 DIN
9 DIN
Propagation Delay Timing
Diagram
-VIN
+VIN = 0V
VOH
VOL
INPUT
tPLH
VS = 50%
0V
tPHL
OUTPUT
+2.5V
-2.5V
AIN
AIN
AOUT
ENABLE
COUT
CIN
CIN
GND
HS9-26C32RH, HS9-26C32EH
(16 LD FLATPACK)
MIL-STD-1835: CDFP4-F16
TOP VIEW
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
VDD
BIN
BIN
BOUT
ENABLE
DOUT
DIN
DIN
Three-State Low Timing Diagram
VIH
VSS
VOZ
VOL
VS INPUT
tPZL
VT
tPLZ
OUTPUT
VW
2 FN3402.5
May 28, 2013







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