Interface Circuit. HS-3282 Datasheet

HS-3282 Circuit. Datasheet pdf. Equivalent

Part HS-3282
Description CMOS ARINC Bus Interface Circuit
Feature HS-3282 REFERENCE AN400 March 1997 CMOS ARINC Bus Interface Circuit Description The HS-3282 is a hi.
Manufacture Intersil Corporation
Datasheet
Download HS-3282 Datasheet




HS-3282
HS-3282
REFERENCE AN400
March 1997
CMOS ARINC Bus Interface Circuit
Features
• ARlNC Specification 429 Compatible
• Data Rates of 100 Kilobits or 12.5 Kilobits
• Separate Receiver and Transmitter Section
• Dual and Independent Receivers, Connecting Directly
to ARINC Bus
• Serial to Parallel Receiver Data Conversion
• Parallel to Serial Transmitter Data Conversion
• Word Lengths of 25 or 32 Bits
• Parity Status of Received Data
• Generate Parity of Transmitter Data
• Automatic Word Gap Timer
• Single 5V Supply
• Low Power Dissipation
• Full Military Temperature Range
Ordering Information
PACKAGE
CERDIP
SMD#
CLCC
SMD#
TEMP. RANGE
-55oC to +125oC
PART NUMBER
HS1-3282-8
PKG.
NO.
F40.6
-40oC to +85oC
-55oC to +125oC
5962-8688001QA
HS4-3282-9+
HS4-3282-8
F40.6
J44.A
J44.A
5962-8688001XA J44.A
Description
The HS-3282 is a high performance CMOS bus interface
circuit that is intended to meet the requirements of ARINC
Specification 429, and similar encoded, time multiplexed
serial data protocols. This device is intended to be used with
the HS-3182, a monolithic Dl bipolar differential line driver
designed to meet the specifications of ARINC 429. The
ARINC 429 bus interface circuit consists of two (2) receivers
and a transmitter operating independently as shown in
Figure 1. The two receivers operate at a frequency that is ten
(10) times the receiver data rate, which can be the same or
different from the transmitter data rate. Although the two
receivers operate at the same frequency, they are
functionally independent and each receives serial data asyn-
chronously. The transmitter section of the ARINC bus
interface circuit consists mainly of a First-In First-Out (FIFO)
memory and timing circuit. The FIFO memory is used to hold
up to eight (8) ARINC data words for transmission serially.
The timing circuit is used to correctly separate each ARINC
word as required by ARINC Specification 429. Even though
ARINC Specification 429 specifies a 32-bit word, including
parity, the HS-3282 can be programmed to also operate with
a word length of 25 bits. The incoming receiver data word
parity is checked, and a parity status is stored in the receiver
latch and output on Pin BD08 during the 1st word. [A logic
“0” indicates that an odd number of logic “1” s were received
and stored; a logic “1” indicates that an even number of logic
“1”s were received and stored]. In the transmitter the parity
generator will generate either odd or even parity depending
upon the status of PARCK control signal. A logic “0” on BD12
will cause odd parity to be used in the output data stream.
Versatility is provided in both the transmitter and receiver by
the external clock input which allows the bus interface circuit
to operate at data rates from 0 to 100 kilobits. The external
clock must be ten (10) times the data rate to insure no data
ambiguity.
The ARINC bus interface circuit is fully guaranteed to
support the data rates of ARINC specification 429 over both
the voltage (±5%) and full military temperature range. It
interfaces with UL, CMOS or NMOS support circuitry, and
uses the standard 5-volt VCC supply.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
5-183
File Number 2964.2



HS-3282
Pinouts
HS-3282
HS-3282 (CERDIP)
TOP VIEW
VDD 1
429DI1(A) 2
429DI1(B) 3
429DI2(A) 4
429DI2(B) 5
D/R1 6
D/R2 7
SEL 8
EN1 9
EN2 10
BD15 11
BD14 12
BD13 13
BD12 14
BD11 15
BD10 16
BD09 17
BD08 18
BD07 19
BD06 20
40 NC
39 MR
38 TX CLK
37 CLK
36 NC
35 NC
34 CWSTR
33 ENTX
32 429D0
31 429D0
30 TX/R
29 PL2
28 PL1
27 BD00
26 BD01
25 BD02
24 BD03
23 BD04
22 BD05
21 GND
HS-3282 (CLCC)
TOP VIEW
6 5 4 3 2 1 44 43 42 41 40
NC 7
39 NC
D/R1 8
38 NC
D/R2 9
37 CWSTR
SEL 10
EN1 11
36 ENTX
35 429D0
EN2 12
34 429D0
BD15 13
33 TX/R
BD14 14
32 PL2
BD13 15
31 PL1
BD12 16
BD11 17
18 19 20 21 22 23 24 25 26 27 28
30 BD00
29 BD01
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