CMOS PROM. HS-6664RH Datasheet

HS-6664RH PROM. Datasheet pdf. Equivalent

Part HS-6664RH
Description Radiation Hardened 8K x 8 CMOS PROM
Feature HS-6664RH September 1995 Radiation Hardened 8K x 8 CMOS PROM Pinouts 5 Features • 1.2 Micron Radia.
Manufacture Intersil Corporation
Datasheet
Download HS-6664RH Datasheet




HS-6664RH
HS-6664RH
September 1995
Radiation Hardened
8K x 8 CMOS PROM
Features
Pinouts
• 1.2 Micron Radiation Hardened Bulk CMOS
• Total Dose 3 x 105 RAD (Si)
• Transient Output Upset >5 x 108 RAD (Si)/s
• LET >100 MEV-cm2/mg
• Fast Access Time - 35ns (Typical)
• Single 5V Power Supply
• Single Pulse 10V Field Programmable
• Synchronous Operation
• On-Chip Address Latches
• Three-State Outputs
• NiCr Fuses
• Low Standby Current <500µA (Pre-Rad)
• Low Operating Current <15mA/MHz
• Military Temperature Range -55oC to +125oC
28 LEAD CERAMIC SBDIP
CASE OUTLINE D28.6 MIL-STD-1835, CDIP2-T28
TOP VIEW
NC 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
DQ0 11
DQ1 12
DQ2 13
GND 14
28 VDD
27 P
26 NC
25 A8
24 A9
23 A11
22 G
21 A10
20 E
19 DQ7
18 DQ6
17 DQ5
16 DQ4
15 DQ3
Description
The Intersil HS-6664RH is a radiation hardened 64K
CMOS PROM, organized in an 8K word by 8-bit for-
mat. The chip is manufactured using a radiation
hardened CMOS process, and utilizes synchronous
circuit design techniques to achieve high speed
performance with very low power dissipation.
On-chip address latches are provided, allowing easy
interfacing with microprocessors that use a
multiplexed address/data bus structure. The output
enable control (G) simplifies system interfacing by
allowing output data bus control in addition to the chip
enable control (E). All bits are manufactured storing a
logical “0” and can be selectively programmed for a
logical “1” at any bit location.
Applications for the HS-6664RH CMOS PROM
include low power microprocessor based instrumenta-
tion and communications systems, remote data acqui-
sition and processing systems, and processor control
storage.
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
28 LEAD FLATPACK
CASE OUTLINE K28.A MIL-STD-1835, CDFP3-F28
TOP VIEW
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
VDD
P
NC
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
† P must be hardwired at all times to VDD, except during programming.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
840
Spec Number 518741
File Number 3197.3



HS-6664RH
Functional Diagram
MSB
A2
A3
A4
A5
A6
A7
A8
LSB
P
LATCHED
ADDRESS
REGISTER
E
A
8
A
8
E
G
HS-6664RH
GATED ROW
DECODER
256
256 X 256
MATRIX
E 32 32 32 32 32 32 32 32
8
GATED COLUMN DECODER
PROGRAMMING, AND DATA
OUTPUT CONTROL
E
A5
A5
E LATCHED ADDRESS
REGISTER
1 OF 8
8
MSB
A0
LSB
A1 A10 A9 A11 A12
† P must be hardwired at all times to VDD, except during programming.
TRUTH TABLE
E G MODE
0 0 Enabled
0 1 Output Disabled
1 X Disabled
Q0 - Q7
Spec Number 518741
841







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