Bus Transceiver. HS-82C08RH Datasheet

HS-82C08RH Transceiver. Datasheet pdf. Equivalent

Part HS-82C08RH
Description Radiation Hardened 8-Bit Bus Transceiver
Feature HS-82C08RH February 1996 Radiation Hardened 8-Bit Bus Transceiver Functional Diagram Features • De.
Manufacture Intersil Corporation
Datasheet
Download HS-82C08RH Datasheet



HS-82C08RH
HS-82C08RH
February 1996
Radiation Hardened
8-Bit Bus Transceiver
Features
Functional Diagram
• Devices QML Qualified in Accordance With
MIL-PRF-38535
• Detailed Electrical and Screening Requirements are
Contained in SMD# 5962-95714 and Intersil’ QM Plan
A0
• Radiation Hardened
- Total Dose 1 x 105 RAD (Si)
- Latch-Up Immune EPI-CMOS > 1 x 1012 RAD (Si)/s
• Bidirectional Three-State Input/Outputs
• Low Propagation Delay Time
• Low Power Consumption
A1
A2
A3
PORT A4
A A5
A6
A7
• Single Power Supply +5V
• Electrically Equivalent to Sandia SA2997
• Military Temperature Range -55oC to +125oC
B0
B1
B2
B3
B4 PORT
B5 B
B6
B7
T/R
Description
The Intersil HS-82C08RH is a radiation-hardened octal bus
transceiver with three-state outputs. It is manufactured using
a self-aligned, junction isolated CMOS process and is
designed for use with the HS-80C08RH radiation-hardened
microprocessor. The HS-82C08RH allows asynchronous
two-way communication between data buses. The direction
of data flow is determined by the logic level on the transmit/
receive (T/R) input. A logic high on the T/R input specifies
data flow from Port A to Port B of the device. Conversely, a
logic low on the T/R input specifies data flow from Port B to
Port A. The Output Enable input disables both ports by
placing them in the high impedance state.
The HS-82C08RH is ideally suited for a wide variety of
buffering applications in radiation-hardened microcomputer
systems.
OE
TRUTH TABLE
INPUTS
OPERATION
OUTPUT
ENABLE
TRANSMIT
/RECEIVE
PORT A PORT B
0 0 Out In
0 1 In Out
1 X High Z High Z
X = Don’t Care
Ordering Information
PART NUMBER
5962R9571401QRC
5962R9571401QXC
5962R9571401VRC
5962R9571401VXC
HS1-82C08RH/SAMPLE
HS9-82C08RH/SAMPLE
TEMPERATURE RANGE
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
+25oC
+25oC
SCREENING LEVEL
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level V
MIL-PRF-38535 Level V
SAMPLE
SAMPLE
PACKAGE
20 Lead SBDIP
20 Lead Ceramic Flatpack
20 Lead SBDIP
20 Lead Ceramic Flatpack
20 Lead SBDIP
20 Lead Ceramic Flatpack
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
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Spec Number 518057
File Number 3040.2



HS-82C08RH
HS-82C08RH
Pinouts
20 LEAD CERAMIC DUAL-IN-LINE
METAL-SEAL PACKAGE (SBDIP) MIL-STD-1835, CDIP2-T20
TOP VIEW
A0 1
A1 2
A2 3
A3 4
A4 5
A5 6
A6 7
A7 8
OE 9
GND 10
20 VDD
19 B0
18 B1
17 B2
16 B3
15 B4
14 B5
13 B6
12 B7
11 T/R
20 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK) MIL-STD-1835, CDFP4-F20
TOP VIEW
A0
A1
A2
A3
A4
A5
A6
A7
OE
GND
1 20
2 19
3 18
4 17
5 16
6 15
7 14
8 13
9 12
10 11
VDD
B0
B1
B2
B3
B4
B5
B6
B7
T/R
PIN
A0-A7
B0-B7
DESCRIPTION
Local Bus Data I/O Pins
System Bus Data I/O Pins
PIN DESCRIPTION
T/R Transmit/Receive Input
OE Active Low Output Enable
Logic Diagram
A0 1
A1 2
A2 3
A3 4
A4 5
OE 9
T/R11
A5 6
B ENABLE
A6 7
A ENABLE
A7 8
TSB
TSB
TSB
TSB
TSB
TSB
TSB
TSB
TSB
TSB
TSB
TSB
TSB
TSB
TSB
TSB
19 B0
18 B1
17 B2
16 B3
15 B4
14 B5
13 B6
12 B7
NOTE: An Important caveat that is applicable to CMOS devices in general is that unused inputs should never be left floating. This rule applies
to inputs connected to a three-state bus. The need for external pull-up resistors during three-state bus conditions is eliminated by the
presence of regenerative latches on the following HS-82C08RH pins. A0-7 and B0-7 The functional block diagram depicts one of
these pins with the regenerative latch. When the CMOS driver assumes the high impedance state, the latch holds the bus in whatever
logic state (high or low) it was before the three-state condition. A transient drive current of ±1.5mA at VDD/2 ±0.5V for 10ns is required
to switch the latch. Thus, CMOS device inputs connected to the bus are not allowed to float during three-state conditions.
Spec Number 518057
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