8-Line Decoder/Demultiplexer. HS1-54C138RH Datasheet

HS1-54C138RH Decoder/Demultiplexer. Datasheet pdf. Equivalent

Part HS1-54C138RH
Description Radiation Hardened 3-Line to 8-Line Decoder/Demultiplexer
Feature HS-54C138RH February 1996 Radiation Hardened 3-Line to 8-Line Decoder/Demultiplexer Pinouts 16 LEAD.
Manufacture Intersil Corporation
Datasheet
Download HS1-54C138RH Datasheet




HS1-54C138RH
HS-54C138RH
February 1996
Radiation Hardened
3-Line to 8-Line Decoder/Demultiplexer
Features
• Devices QML Qualified in Accordance With
MIL-PRF-38535
• Detailed Electrical and Screening Requirements are
Contained in SMD# 5962-95825 and Intersil’ QM Plan
• Radiation Hardened EPI-CMOS
- Total Dose 1 x 105 RAD (Si)
- Latch-Up Immune > 1 x 1012 RAD (Si)/s
• Multiple Input Enable for Easy Expansion
• Single Power Supply +5V
• Outputs Active Low
• Low Standby Power (0.5mW Max at +5V)
• High Noise Immunity
• Equivalent to Sandia SA2995
• Bus Compatible with Intersil Rad-Hard 80C85RH
• Full Military Temperature Range -55oC to +125oC
Pinouts
16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T16
TOP VIEW
A1
B2
C3
G2A 4
G2B 5
G1 6
Y7 7
GND 8
16 VDD
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
9 Y6
Description
The Intersil HS-54C138RH is a radiation hardened 3- to 8-line
decoder fabricated using a radiation hardened EPI-CMOS pro-
cess. It features low power consumption, high noise immunity,
and high speed. Also featured are pin and function compatibility
with the 54LS138 industry standard part. The HS-54C138RH is
ideally suited for high speed memory chip select address
decoding. It is intended for use with the Intersil HS-80C85RH
radiation hardened microprocessor, but it can also be utilized as
a demultiplexer in any low power rad-hard application.
The HS-54C138RH contains a one of eight binary decoder.
A three bit binary input is used to select and activate each of
the eight outputs, provided the three chip enable inputs are
also present (see truth table).
The HS-54C138RH has an on-chip enable gate. The active
high (G1) and both active low (G2A, G2B) inputs are Anded
together to provide a single enable input to the device. The
use of both active high and active low inputs minimizes the
need for external gates when expanding a system.
A
B
C
G2A
G2B
G1
Y7
GND
16 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F16
TOP VIEW
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
VDD
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Ordering Information
PART NUMBER
5962R9582501QEC
5962R9582501QXC
5962R9582501VEC
5962R9582501VXC
HS1-54C138RH/SAMPLE
HS9-54C138RH/SAMPLE
TEMPERATURE RANGE
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
+25oC
+25oC
SCREENING LEVEL
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level V
MIL-PRF-38535 Level V
Sample
Sample
PACKAGE
16 Lead SBDIP
16 Lead Ceramic Flatpack
16 Lead SBDIP
16 Lead Ceramic Flatpack
16 Lead SBDIP
16 Lead Ceramic Flatpack
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
Spec Number 518053
File Number 3037.2



HS1-54C138RH
Specifications HS-54C138RH
Absolute Maximum Ratings
Reliability Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
I/O Voltage Applied. . . . . . . . . . . . . . . . . . GND -0.3V to VDD +0.3V
Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance
θJA θJC
SBDIP Package . . . . . . . . . . . . . . . . . . . . 73oC/W 24oC/W
Ceramic Flatpack Package . . . . . . . . . . . 114oC/W 29oC/W
Maximum Package Power Dissipation at +125oC Ambient
SBDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.44W
If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:
SBDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7mW/oC
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 8.8mW/oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 1.0V
Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . VDD-1.0V to VDD
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Input Leakage Current
High
Input Leakage Current
Low
High Level Output
Voltage
Low Level Output
Voltage
Static Current
SYMBOL
CONDITIONS
IIH VDD = 5.25V, VIN = 0V,
Pin Under Test = VDD
IIL VDD = 5.25V, VIN = 5.25V,
Pin Under Test = 0V
VOH VDD = 4.75V, IIN = -2mA
VOL VDD = 5.25V, IIN = 2mA
SIDD VDD = 5.25V, VIN = GND
Functional Tests
FT VDD = 5.25V and 4.75V,
VIH = VDD - 1.0V, VIL = 1.0V
NOTE: All devices are guaranteed at worst case limits and conditions.
GROUP A
SUBGROUPS
1, 2, 3
1, 2, 3
TEMPERATURE
-55oC, +25oC,
+125oC
-55oC, +25oC
LIMITS
MIN MAX
-1
-1 -
UNITS
µA
µA
1, 2, 3
1, 2, 3
1, 2, 3
7, 8A, 8B
-55oC, +25oC,
+125oC
-55oC, +25oC,
+125oC
-55oC, +25oC,
+125oC
-55oC, +25oC,
+125oC
4.25 -
0.5 -
- 100
--
V
V
µA
-
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
GROUP A SUB-
GROUPS
SELECT TO OUTPUT PROPAGATION DELAY TIME
Low to high level input, High to
low level output
TPHL11
9, 10, 11
Low to high level input, Low to
high level output
TPLH11
9, 10, 11
High to low level input, Low to
high level output
TPLH12
9, 10, 11
High to low level input, high to
low level output
TPHL12
9, 10, 11
ENABLE TO OUTPUT PROPAGATION DELAY TIME
Low to high level input, Low to
high level output
TPLH21
9, 10, 11
TEMPERATURE
-55oC, +25oC, +125oC
-55oC, +25oC, +125oC
-55oC, +25oC, +125oC
-55oC, +25oC, +125oC
-55oC, +25oC, +125oC
LIMITS
MIN MAX
- 110
- 65
- 75
- 90
- 70
UNITS
ns
ns
ns
ns
ns
Spec Number 518053
2







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)