Digital-to-Analog Converter. HS1-565ARH-T Datasheet

HS1-565ARH-T Converter. Datasheet pdf. Equivalent

Part HS1-565ARH-T
Description Radiation Hardened High Speed/ Monolithic Digital-to-Analog Converter
Feature HS-565ARH-T Data Sheet July 1999 File Number 4607.1 Radiation Hardened High Speed, Monolithic Digit.
Manufacture Intersil Corporation
Datasheet
Download HS1-565ARH-T Datasheet



HS1-565ARH-T
Data Sheet
HS-565ARH-T
July 1999 File Number 4607.1
Radiation Hardened High Speed,
Monolithic Digital-to-Analog Converter
Intersil’s Satellite Applications FlowTM (SAF) devices are fully
tested and guaranteed to 100kRAD total dose. This QML
Class T device is processed to a standard flow intended to
meet the cost and shorter lead-time needs of large volume
satellite manufacturers, while maintaining a high level of
reliability.
The HS-565ARH-T is a fast, radiation hardened 12-bit
current output, digital-to-analog converter. The monolithic
chip includes a precision voltage reference, thin-film R-2R
ladder, reference control amplifier and twelve high-speed
bipolar current switches.
The Intersil Semiconductor Dielectric Isolation process
provides latch-up free operation while minimizing stray
capacitance and leakage currents, to produce an excellent
combination of speed and accuracy. Also, ground currents
are minimized to produce a low and constant current through
the ground terminal, which reduces error due to code-
dependent ground currents.
HS-565ARH-T die are laser trimmed for a maximum integral
nonlinearity error of ±0.25 LSB at 25oC. In addition, the low
noise buried zener reference is trimmed both for absolute value
and minimum temperature coefficient.
Specifications
Specifications for Rad Hard QML devices are controlled by
the Defense Supply Center in Columbus (DSCC). The SMD
numbers listed below must be used when ordering.
Detailed Electrical Specifications for the HS-565ARH-T
are contained in SMD 5962-96755. A “hot-link” is provided
from our website for downloading.
www.intersil.com/spacedefense/newsafclasst.asp
Intersil‘s Quality Management Plan (QM Plan), listing all
Class T screening operations, is also available on our
website.
www.intersil.com/quality/manuals.asp
Ordering Information
ORDERING
NUMBER
PART
NUMBER
TEMP.
RANGE
(oC)
5962R9675501TJC
HS1-565ARH-T
-55 to 125
5962R9675501TXC
HS9-565ARH-T
-55 to 125
NOTE: Minimum order quantity for -T is 150 units through
distribution, or 450 units direct.
Features
• qml Class T, Per MIL-PRF-38535
• Radiation Performance
- Gamma Dose (γ) 1 x 105 RAD(Si)
- No Latch-Up, Dielectrically Isolated Device Islands
• DAC and Reference on a Single Chip
• Pin Compatible with AD-565A and HI-565A
• Very High Speed: Settles to 0.50 LSB in 500ns Max
• Monotonicity Guaranteed Over Temperature
• 0.50 LSB Max Nonlinearity Guaranteed Over Temperature
• Low Gain Drift (Max., DAC Plus Reference) 50ppm/oC
±0.75 LSB Accuracy Guaranteed Over Temperature
(±0.125 LSB Typical at 25oC)
Pinouts
HS1-565ARH-T (SBDIP), CDIP2-T24
TOP VIEW
NC 1
NC 2
VCC 3
REF OUT 4
REF GND 5
REF IN 6
-VEE 7
BIPOLAR RIN 8
IDAC OUT 9
10V SPAN 10
20V SPAN 11
PWR GND 12
24 BIT 1 IN (MSB)
23 BIT 2 IN
22 BIT 3 IN
21 BIT 4 IN
20 BIT 5 IN
19 BIT 6 IN
18 BIT 7 IN
17 BIT 8 IN
16 BIT 9 IN
15 BIT 10 IN
14 BIT 11 IN
13 BIT 12 IN (LSB)
HS9-565ARH-T (FLATPACK), CDFP4-F24
TOP VIEW
NC
NC
VCC
REF OUT
REF GND
REF IN
-VEE
BIPOLAR RIN
IDAC OUT
10V SPAN
20V SPAN
PWR GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
BIT 1 IN
(MSB)
BIT 2 IN
BIT 3 IN
BIT 4 IN
BIT 5 IN
BIT 6 IN
BIT 7 IN
BIT 8 IN
BIT 9 IN
BIT 10 IN
BIT 11 IN
BIT 12 IN
(LSB)
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
Satellite Applications Flow™ (SAF) is a trademark of Intersil Corporation.



HS1-565ARH-T
HS-565ARH-T
Functional Diagram
REF OUT VCC
43
+
-
REF 6 19.95K
IN
REF 5
GND
10V
IREF
0.5mA
3.5K
+
-
3K
BIP.
OFF.
8
9.95K
DAC
IO
(4X IREF
X CODE)
11 20V
SPAN
5K
10 10V
SPAN
5K
9
OUT
2.5K
7 12
-VEE PWR
GND
24. . . 13
MSB LSB
Definitions of Specifications
Digital Inputs
The HS-565ARH-T accepts digital input codes in binary
format and may be user connected for any one of three
binary codes. Straight binary, Two’s Complement (see note
below), or Offset Binary, (see Operating Instructions).
DIGITAL
INPUT
MSB . LSB
ANALOG OUTPUT
STRAIGHT
BINARY
OFFSET
BINARY
(NOTE)
TWO’S
COMPLEMENT
000 . . . 000
Zero
- fS (Full Scale)
Zero
100 . . . 000
0.50 fS
Zero
- fS
111 . . . 111 + fS - 1 LSB + fS - 1 LSB
Zero - 1 LSB
011 . . . 111 0.50 fS - 1 LSB Zero - 1 LSB
+ fS - 1 LSB
NOTE: Invert MSB with external inverter to obtain Two’s
Complement Coding.
Accuracy
Nonlinearity - Nonlinearity of a D/A converter is an
important measure of its accuracy. It describes the deviation
from an ideal straight line transfer curve drawn between zero
(all bits OFF) and full scale (all bits ON).
Differential Nonlinearity - For a D/A converter, it is the
difference between the actual output voltage change and the
ideal (1 LSB) voltage change for a one bit change in code. A
Differential Nonlinearity of ±1 LSB or less guarantees
monotonicity; i.e., the output always increases and never
decreases for an increasing input.
Settling Time
Settling time is the time required for the output to settle to
within the specified error band for any input code transition.
It is usually specified for a full scale or major carry transition,
settling to within 0.50 LSB of final value.
Drift
Gain Drift - The change in full scale analog output over the
specified temperature range expressed in parts per million of
full scale range per oC (ppm of FSR/oC). Gain error is
measured with respect to 25oC at high (tH) and low (tL)
temperatures. Gain drift is calculated for both high (tL -
25oC) and low ranges (25oC - tL) by dividing the gain error
by the respective change in temperature. The specification is
the larger of the two representing worst case drift.
Offset Drift - The change in analog output with all bits OFF
over the specified temperature range expressed in parts per
million of full scale range per oC (ppm of FSR/oC). Offset
error is measured with respect to 25oC at high (tH) and low
(tL) temperatures. Offset drift is calculated for both high (tD -
25oC) and low (25oC - tL) ranges by dividing the offset error
by the respective change in temperature. The specification
given is the larger of the two, representing worst case drift.
Power Supply Sensitivity
Power Supply Sensitivity is a measure of the change in
gain and offset of the D/A converter resulting from a
change in -15V or +15V supplies. It is specified under DC
conditions and expressed as parts per million of full scale
range per percent of change in power supply (ppm of
FSR/%).
Compliance
Compliance Voltage is the maximum output voltage range
that can be tolerated and still maintain its specified accuracy.
Compliance Limit implies functional operation only and
makes no claims to accuracy.
Glitch
A glitch on the output of a D/A converter is a transient spike
resulting from unequal internal ON-OFF switching times.
Worst case glitches usually occur at half scale or the major
carry code transition from 011 . . . 1 to 100 . . . 0 or vice
versa. For example, if turn ON is greater than turn OFF for
011 . . . 1 to 100 . . . 0, an intermediate state of 000 . . . 0
exists, such that, the output momentarily glitches toward
zero output. Matched switching times and fast switching will
reduce glitches considerably.
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