Interval Timer. HS1-82C54RH-Q Datasheet

HS1-82C54RH-Q Timer. Datasheet pdf. Equivalent

Part HS1-82C54RH-Q
Description Radiation Hardened CMOS Programmable Interval Timer
Feature HS-82C54RH August 1995 Radiation Hardened CMOS Programmable Interval Timer Pinouts 24 LEAD CERAMIC .
Manufacture Intersil Corporation
Datasheet
Download HS1-82C54RH-Q Datasheet




HS1-82C54RH-Q
HS-82C54RH
August 1995
Radiation Hardened CMOS
Programmable Interval Timer
Features
Pinouts
• Radiation Hardened
- Total Dose > 105 RAD (Si)
- Transient Upset > 108 RAD (Si)/sec
- Latch Up Free EPI-CMOS
- Functional After Total Dose 1 x 106 RAD (Si)
• Low Power Consumption
- IDDSB = 20µA
- IDDOP = 12mA
• Pin Compatible with NMOS 8254 and the Intersil 82C54
• High Speed, “No Wait State” Operation with 5MHz
HS-80C86RH
• Three Independent 16-Bit Counters
• Six Programmable Counter Modes
• Binary or BCD Counting
• Status Read Back Command
• Hardened Field, Self-Aligned, Junction Isolated CMOS Process
• Single 5V Supply
• Military Temperature Range -55oC to +125oC
Description
The Intersil HS-82C54RH is a high performance, radiation hardened
CMOS version of the industry standard 8254 and is manufactured
using a hardened field, self-aligned silicon gate CMOS process. It has
three independently programmable and functional 16-bit counters,
each capable of handling clock input frequencies of up to 5MHz. Six
programmable timer modes allow the HS-82C54RH to be used as an
event counter, elapsed time indicator, a programmable one-shot, or
for any other timing application. The high performance, radiation
hardness, and industry standard configuration of the HS-82C54RH
make it compatible with the HS-80C86RH radiation hardened micro-
processor.
Static CMOS circuit design insures low operating power. The Intersil
hardened field CMOS process results in performance equal to or
greater than existing radiation resistant products at a fraction of the
power.
24 LEAD CERAMIC DUAL-IN-LINE METAL SEAL
PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T24
TOP VIEW
D7 1
D6 2
D5 3
D4 4
D3 5
D2 6
D1 7
D0 8
CLK 0 9
OUT 0 10
GATE 0 11
GND 12
24 VDD
23 WR
22 RD
21 CS
20 A1
19 A0
18 CLK 2
17 OUT 2
16 GATE 2
15 CLK 1
14 GATE 1
13 OUT 1
24 LEAD CERAMIC METAL SEAL FLATPACK
PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F24
TOP VIEW
D7
D6
D5
D4
D3
D2
D1
D0
CLK 0
OUT 0
GATE 0
GND
1
2
3
4
5
6
7
8
9
10
11
12
24 VDD
23 WR
22 RD
21 CS
20 A1
19 A0
18 CLK 2
17 OUT 2
16 GATE 2
15 CLK 1
14 GATE 1
13 OUT1
Ordering Information
PART NUMBER
HS1-82C54RH-Q
HS1-82C54RH-8
HS1-82C54RH-Sample
HS9-82C54RH-Q
HS9-82C54RH-8
HS9-82C54RH/Sample
HS9-82C54RH/Proto
TEMPERATURE RANGE
-55oC to +125oC
-55oC to +125oC
+25oC
-55oC to +125oC
-55oC to +125oC
+25oC
-55oC to +125oC
PACKAGE
24 Lead SBDIP
24 Lead SBDIP
24 Lead SBDIP
24 Lead Ceramic Flatpack
24 Lead Ceramic Flatpack
24 Lead Ceramic Flatpack
24 Lead Ceramic Flatpack
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
948
Spec Number 518059
File Number 3043.1



HS1-82C54RH-Q
HS-82C54RH
Pin Description
SYMBOL
D7-D0
CLK 0
OUT 0
GATE 0
GND
OUT 1
GATE 1
CLK 1
GATE 2
OUT 2
CLK 2
A0, A1
PIN
NUMBER
1-8
9
10
11
12
13
14
15
16
17
18
19-20
CS
RD
WR
VDD
21
22
23
24
TYPE
I/O
I
O
I
O
I
I
I
O
I
I
I
I
I
DESCRIPTION
DATA: Bi-directional three state data bus lines, connected to system data bus.
CLOCK 0: Clock input of Counter 0.
OUT 0: Output of Counter 0.
GATE 0: Gate input of Counter 0.
GROUND: Power supply connection.
OUT 1: Output of Counter 1.
GATE 1: Gate input of Counter 1.
CLOCK 1: Clock input of Counter 1.
GATE 2: Gate input of Counter 2.
OUT 2: Output of Counter 2.
CLOCK 2: Clock input of Counter 2.
ADDRESS: Select inputs for one of the three counters or Control Word Register for read/write
operations. Normally connected to the system address bus.
A1 A0 Selects
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control Word Register
CHIP SELECT: A low on this input enables the HS-82C54RH to respond to RD and WR signals.
RD and WR are ignored otherwise.
READ: This input is low during CPU read operations.
WRITE: This input is low during CPU write operations.
VDD: The +5V power supply pin. A 0.1µF capacitor between pins 12 and 24 is recommended
for decoupling.
Functional Diagram
INTERNAL BUS
D7-D0 (8)
DATA
BUS
BUFFER
RD
WR
READ/
WRITE
A0 LOGIC
A1
CS
CONTROL
WORD
REGISTER
COUNTER
0
COUNTER
1
COUNTER
2
CLK 0
GATE 0
OUT 0
CONTROL
WORD
REGISTER
STATUS
LATCH
CLK 1
GATE 1
OUT 1
STATUS
REGISTER
CONTROL
LOGIC
CLK 2
GATE 2
OUT 2
GATE N
CLK N OUT N
CRM
CRL
CE
OLM
OLL
Spec Number 518059
949







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)