Peripheral Interface. HS1-82C55ARH-8 Datasheet

HS1-82C55ARH-8 Interface. Datasheet pdf. Equivalent

Part HS1-82C55ARH-8
Description Radiation Hardened CMOS Programmable Peripheral Interface
Feature HS-82C55ARH September 1995 Radiation Hardened CMOS Programmable Peripheral Interface Pinout 40 LEAD.
Manufacture Intersil Corporation
Datasheet
Download HS1-82C55ARH-8 Datasheet



HS1-82C55ARH-8
HS-82C55ARH
September 1995
Radiation Hardened
CMOS Programmable Peripheral Interface
Features
Pinout
• Radiation Hardened
- Total Dose >105 RAD (Si)
- Transient Upset <108 RAD (Si)/s
- Latch Up Free EPI-CMOS
• Low Power Consumption
- IDDSB = 20µA
• Pin Compatible with NMOS 8255A and the Intersil 82C55A
• High Speed, No “Wait State” Operation with 5MHz HS-80C86RH
• 24 Programmable I/O Pins
• Bus-Hold Circuitry on All I/O Ports Eliminates Pull-Up Resistors
• Direct Bit Set/Reset Capability
• Enhanced Control Word Read Capability
• Hardened Field, Self-Aligned, Junction Isolated CMOS Process
• Single 5V Supply
• 2.0mA Drive Capability on All I/O Port Outputs
• Military Temperature Range: -55oC to +125oC
Description
The Intersil HS-82C55ARH is a high performance, radiation hardened
CMOS version of the industry standard 8255A and is manufactured using a
hardened field, self-aligned silicongate CMOS process. It is a general
purpose programmable I/O device which may be used with many different
microprocessors. There are 24 I/O pins which are organized into two 8-bit
and two 4-bit ports. Each port may be programmed to function as either an
input or an output. Additionally, one of the 8-bit ports may be programmed
for bi-directional operation,and the two 4-bit ports can be programmed to
provide handshaking capabilities. The high performance, radiation
hardness, and industry standard configuration of the HS-82C55ARH make
it compatible with the HS-80C86RH radiation hardened microprocessor.
Static CMOS circuit design insures low operating power. Bus hold circuitry
eliminates the need for pull-up resistors. The Intersil hardened field CMOS
process results in performance equal to or greater than existing radiation
resistant products at a fraction of the power.
40 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T40
TOP VIEW
PA3
PA2
PA1
PA0
RD
CS
GND
A1
A0
PC7
PC6
PC5
PC4
PC0
PC1
PC2
PC3
PB0
PB1
PB2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 PA4
39 PA5
38 PA6
37 PA7
36 WR
35 RESET
34 D0
33 D1
32 D2
31 D3
30 D4
29 D5
28 D6
27 D7
26 VDD
25 PB7
24 PB6
23 PB5
22 PB4
21 PB3
Pin Description
PIN
D7 - D0
RESET
CS
RD
WR
DESCRIPTION
Data Bus (Bi-Directional
Reset Input
Chip Select
Read Input
Write Input
Ordering Information
A0 - A1
Port Address
PART NUMBER
HS1-82C55ARH-Q
HS1-82C55ARH-8
HS1-82C55ARH/Sample
TEMPERATURE
-55oC to +125oC
-55oC to +125oC
+25oC
PACKAGE
40 Lead SBDIP
40 Lead SBDIP
40 Lead SBDIP
PA7 - PA0
PB& - PB0
PC7 - PC0
VDD
GND
Port A (Bit)
Port B (Bit)
Port C (Bit)
+5 volts
0 volts
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
970
Spec Number 518060
File Number 3191.1



HS1-82C55ARH-8
Pin Description
SYMBOL
PA0-7
PIN
NUMBERS
1-4, 37-40
PB0-7
PC0-3
PC4-7
D0-7
18-25
14-17
10-13
27-34
VDD
26
GND
CS
7
6
RD 5
WR
A0 and A1
36
8, 9
Reset
35
HS-82C55ARH
TYPE
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
DESCRIPTION
Port A: General purpose I/O Port. Data direction and mode is determined by the contents
of the Control Word.
Port B: General purpose I/O port. See Port A.
Port C (Lower): Combination I/O port and control port associated with Port B. See Port A.
Port C (Upper): Combination I/O Port and control port associated with Port A. See Port A.
Bidirectional Data Bus: Three-State data bus enabled as an input when CS and WR are
low and as an output when CS and RD are low.
VDD: The +5V power supply pin. A 0.1µF capacitor between pins 26 and 7 is recommend-
ed for decoupling.
Ground.
Chip Select: A “low” on this input pin enables the communication between the
HS-82C55ARH and the CPU.
Read: A “low” on this input pin enables the HS-82C55ARH to send the data or status
information to the CPU on the data bus. In essence, it allows the CPU to “read from” the
HS-82C55ARH.
Write: A “low” on this input pin enables the CPU to write data or control words into the
HS-82C55ARH.
Port Select 0 and Port Select 1: These input signals, in conjunction with the RD and WR
inputs, control the selection of one of the three ports or the control word registers. They are
normally connected to the Least Significant Bits of the address bus (A0 and A1).
Reset: A “high” on this input clears the control register and all ports (A, B, C) are set to the
input mode. “Bus hold” devices internal to the HS-82C55ARH will hold the I/O port inputs
to a logic “1” state with a maximum hold current of 400µA.
Functional Diagram
POWER
SUPPLIES
+5V
GND
GROUP A
CONTROL
GROUP A
PORT A
(8)
I/O
PA7 - PA0
BIDIRECTIONAL
DATA BUS
D7 - D0
DATA
BUS
BUFFER
RD
WR
A1
A0
RESET
CS
READ/WRITE
CONTROL
LOGIC
8-BIT INTERNAL
DATA BUS
GROUP B
CONTROL
971
GROUP A
PORT C
UPPER (4)
GROUP B
PORT C
LOWER (4)
I/O
PC7 - PC4
I/O
PC3 - PC0
GROUP B
PORT B
(8)
I/O
PB7 - PB0
Spec Number 518060







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