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HS9-80C86RH Dataheets PDF



Part Number HS9-80C86RH
Manufacturers Intersil Corporation
Logo Intersil Corporation
Description Radiation Hardened 16-Bit CMOS Microprocessor
Datasheet HS9-80C86RH DatasheetHS9-80C86RH Datasheet (PDF)

HS-80C86RH September 1995 Radiation Hardened 16-Bit CMOS Microprocessor Description The Intersil HS-80C86RH high performance radiation hardened 16-bit CMOS CPU is manufactured using a hardened field, self aligned silicon gate CMOS process. Two modes of operation, MINimum for small systems and MAXimum for larger applications such as multiprocessing, allow user configuration to achieve the highest performance level. Industry standard operation allows use of existing NMOS 8086 hardware and software .

  HS9-80C86RH   HS9-80C86RH



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HS-80C86RH September 1995 Radiation Hardened 16-Bit CMOS Microprocessor Description The Intersil HS-80C86RH high performance radiation hardened 16-bit CMOS CPU is manufactured using a hardened field, self aligned silicon gate CMOS process. Two modes of operation, MINimum for small systems and MAXimum for larger applications such as multiprocessing, allow user configuration to achieve the highest performance level. Industry standard operation allows use of existing NMOS 8086 hardware and software designs. Features • Radiation Hardened - Latch Up Free EPl-CMOS - Total Dose >100K RAD (Si) - Transient Upset >108 RAD (Si)/s • Low Power Operation - ICCSB = 500µA (Max) - ICCOP = 12mA/MHz (Max) • Pin Compatible with NMOS 8086 and Intersil 80C86 • Completely Static Design DC to 5MHz • 1MB Direct Memory Addressing Capability • 24 Operand Addressing Modes • Bit, Byte, Word, and Block Move Operations • 8-Bit and 16-Bit Signed/Unsigned Arithmetic - Binary or Decimal - Multiply and Divide • Bus-hold Circuitry Eliminates Pull-up Resistors for CMOS Designs • Hardened Field, Self-Aligned, Junction-Isolated CMOS Process • Single 5V Power Supply • Military Temperature Range -35oC to +125oC • Minimum LET for Single Event Upset -6MEV/mg/cm2 (Typ) Ordering Information PART NUMBER HS1-80C86RH-8 HS1-80C86RH-Q HS9-80C86RH-8 HS9-80C86RH-Q HS9-80C86RH-SAMPLE HS1-80C86RH-SAMPLE HS9-80C86RH-PROTO HS1-80C86RH-PROTO TEMPERATURE RANGE -35o C to +125o C -35o C to +125o C -35o C to +125o C -35o C to +125o C 25o C 25o C -35o C to +125o C -35o C to +125o C SCREENING LEVEL Intersil Class B Equivalent Intersil Class S Equivalent Intersil Class B Equivalent Intersil Class S Equivalent Sample Sample Prototype Prototype PACKAGE 40 Lead Braze Seal DIP 40 Lead Braze Seal DIP 42 Lead Braze Seal Flatpack 42 Lead Braze Seal Flatpack 42 Lead Braze Seal Flatpack 40 Lead Braze Seal DIP 42 Lead Braze Seal Flatpack 40 Lead Braze Seal DIP CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 Spec Number File Number 856 518055 3035.1 HS-80C86RH Pinouts HS-80C86RH 40 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835, CDIP2-T40 TOP VIEW MAX 40 VDD 39 AD15 38 AD16/S3 37 A17/S4 36 A18/S5 35 A19/S6 34 BHE/S7 33 MN/MX 32 RD 31 RQ/GT0 30 RQ/GT1 29 LOCK 28 S2 27 S1 26 S0 25 QS0 24 QS1 23 TEST 22 READY 21 RESET (HOLD) (HLDA) (WR) (M/IO) (DT/R) (DEN) (ALE) (INTA) MIN GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 HS-80C86RH 42 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) INTERSIL OUTLINE K42.A TOP VIEW GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NC NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 MAX VDD AD15 NC A16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 MN/MX RD RQ/GT0 RQ/GT1 LOCK S2 S1 S0 QS0 QS1 TEST READY RESET MIN (HOLD) (HLDA) (WR) (M/IO) (DT/R) (DEN) (ALE) (INTA) Spec Number 857 518055 HS-80C86RH Functional Diagram BUS INTERFACE UNIT EXECUTION UNIT REGISTER FILE DATA POINTER AND INDEX REGS (8 WORDS) RELOCATION REGISTER FILE SEGMENT REGISTERS AND INSTRUCTION POINTER (5 WORDS) 16-BIT ALU FLAGS BUS INTERFACE UNIT 4 16 3 4 BHE/S7 A19/S6 A16/S3 AD15-AD0 INTA, RD, WR DT/R, DEN, ALE, M/IO 6-BYTE INSTRUCTION QUEUE TEST INTR NMI RQ/GT0, 1 HOLD HLDA 3 GND VDD 2 CONTROL AND TIMING LOCK 2 3 QS0, QS1 S2, S1, S0 CLK RESET READY MN/MX MEMORY INTERFACE C-BUS B+BUS ES BUS INTERFACE UNIT CS SS DS IP INSTRUCTION STREAM BYTE QUEUE EXECUTION UNIT CONTROL SYSTEM A-BUS AH BH CH EXECUTION UNIT DH SP BP SI DI AL BL CL DL ARITHMETIC/ LOGIC UNIT FLAGS Spec Number 858 518055 HS-80C86RH Pin Description SYMBOL PIN NUMBER TYPE DESCRIPTION The following pin function descriptions are for HS-80C86RH systems in either minimum or maximum mode. The “Local Bus” in these descriptions is the direct multiplexed bus interface connection to the HS-80C86RH (without regard to additional bus buffers). AD15-AD0 2-16, 39 I/O ADDRESS DATA BUS: These lines constitute the time multiplexed memory/IO address (T1) and data (T2, T3, TW, T4) bus. AO is analogous to BHE for the lower byte of the data bus, pins D7-D0. It is LOW during T1 when a byte is to be transferred on the lower portion of the bus in memory or I/O operations. Eight-bit oriented devices tied to the lower half would normally use AD0 to condition chip select functions (See BHE). These lines are active HIGH and are held at high impedance to the last valid logic level during interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”. ADDRESS/STATUS: During T1, these are the four most significant address lines for memory operations. During I/O operations these lines are low. During memory and I/O operations, status information is available on these lines during T2, T3, .


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