Document
HN29W12811 Series
128M AND type Flash Memory More than 8,029-sector (135,657,984-bit)
ADE-203-1183C (Z) Rev. 2.0 Feb. 7, 2001 Description
The Hitachi HN29W12811 Series is a CMOS Flash Memory with AND type multi-level memory cells. It has fully automatic programming and erase capabilities with a single 3.3 V power supply. The functions are controlled by simple external commands. To fit the I/O card applications, the unit of programming and erase is as small as (2048 + 64) bytes. Initial available sectors of HN29W12811 are more than 8,029 (98% of all sector address).
Features
• On-board single power supply (VCC): VCC = 3.3 V ± 0.3 V • Organization AND Flash Memory: (2048 + 64) bytes × (More than 8,029 sectors) Data register: (2048 + 64) bytes • Multi-level memory cell 2 bit/per memory cell • Automatic programming Sector program time: 2.5 ms (typ) System bus free Address, data latch function Internal automatic program verify function Status data polling function • Automatic erase Single sector erase time: 1.0 ms (typ) System bus free Internal automatic erase verify function Status data polling function
HN29W12811 Series
• Erase mode Single sector erase ((2048 + 64) byte unit) • Fast serial read access time: First access time: 50 µs (max) Serial access time: 60 ns (max) • Low power dissipation: ICC2 = 40 mA (max) (Read) ISB2 = 50 µA (max) (Standby) ICC3/ICC4 = 40 mA (max) (Erase/Program) ISB3 = 5 µA (max) (Deep standby) • The following architecture is required for data reliability. Error correction: more than 1-bit error correction per each sector read Spare sectors: 1.8% (145 sectors) within usable sectors
Ordering Information
Type No. HN29W12811T-60 Available sector More than 8,029 sectors Package 12.0 × 18.40 mm 2 0.5 mm pitch 48-pin plastic TSOP I (TFP-48DA)
2
HN29W12811 Series
Pin Arrangement
48-pin TSOP VCC VSS VSS VSS VSS RES RDY/Busy SC OE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 CDE WE CE VSS VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (Top view) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
Pin Description
Pin name I/O0 to I/O7 CE OE WE CDE VCC* VSS *
1 1
Function Input/output Chip enable Output enable Write enable Command data enable Power supply Ground Ready/ Busy Reset Serial clock
RDY/Busy RES SC Note:
1. All V CC and VSS pins should be connected to a common power supply and a ground, respectively.
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HN29W12811 Series
Block Diagram
2048 + 64
Sector address buffer
X-decoder
8192 × (2048 + 64) × 8 memory matrix
•• I/O0 to I/O7 Data input buffer Input data control
Data register (2048 + 64)
• •
• Multiplexer •
• •
• •
Y-gating Y-decoder
Data output buffer •••
RDY/Busy
•• • • Y-address counter
VCC VSS
CE OE WE SC RES CDE Control signal buffer Read/Program/Erase control
4
8029 - 8192
HN29W12811 Series
Memory Map and Address
Sector address 2048 bytes 1FFFH 1FFEH 1FFDH 2048 bytes 2048 bytes 64 bytes 64 bytes 64 bytes
2048 bytes 0002H 0001H 0000H 000H 2048 + 64 bytes 2048 bytes 2048 bytes
64 bytes 64 bytes 64 bytes 800H 83FH Column address
Control bytes Cycles SA (1): SA (2): Column address CA (1): CA (2): Address Sector address I/O0 I/O1 I/O2 I/O3 A0 A1 A2 A3 A8 A9 A10 A11 A0 A1 A2 A3 A8 A9 A10 A11 I/O4 I/O5 I/O6 I/O7 A4 A5 A6 A7 A12 ×*2 × × A4 A5 A6 A7 × × × ×
First cycle Second cycle First cycle Second cycle
Notes: 1. Some failed sectors may exist in the device. The failed sectors can be recognized by reading the sector valid data written in a part of the column address 800 to 83F (The specific address is TBD.). The sector valid data must be read and kept outside of the sector before the sector erase. When the sector is programmed, the sector valid data should be written back to the sector. 2. An × means "Don't care". The pin level can be set to either VIL or VIH, referred to DC characteristics.
8029 - 8192 sectors *1
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HN29W12811 Series
Pin Function
CE: CE is used to select the device. The status returns to the standby at the rising edge of CE in the reading operation. However, the status does not return to the standby at the rising edge of CE in the busy state in programming and erase operation. OE: Memory data and status register data can be read, when OE is VIL . WE : Commands and address are latched at the rising edge of WE. SC: Programming and reading data is latched at the rising edge of SC. RES : RES pin must be kept at the VILR (V SS ± 0.2 V) level when VCC is turned on and off. In this way, data in the memory is protected against unintentional erase and programming. RES must be kept at the VIHR (VCC ± 0.2 V) level during any operations such as programming, erase and read. CDE: Commands and data are latched when CDE is VIL and address is latched when CDE is VIH. RDY/Busy: The RDY/Busy indicates the program/erase status of the flash memory. The RDY/ Busy signal is initially at a high impeda.