CMOS RAM. HM-6551 Datasheet

HM-6551 RAM. Datasheet pdf. Equivalent


Intersil Corporation HM-6551
HM-6551/883
March 1997
256 x 4 CMOS RAM
Features
Description
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Low Power Standby . . . . . . . . . . . . . . . . . . . . 50µW Max
• Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max
• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 220ns Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min
• TTL Compatible Input/Output
• High Output Drive - 1 TTL Load
• Internal Latched Chip Select
• High Noise Immunity
• On-Chip Address Register
• Latched Outputs
• Three-State Output
The HM-6551/883 is a 256 x 4 static CMOS RAM fabricated
using self-aligned silicon gate technology. Synchronous cir-
cuit design techniques are employed to achieve high perfor-
mance and low power operation. On chip latches are
provided for address and data outputs allowing efficient
interfacing with microprocessor systems. The data output
buffers can be forced to a high impedance state for use in
expanded memory arrays.
The HM-6551/883 is a fully static RAM and may be main-
tained in any state for an indefinite period of time. Data
retention supply voltage and supply current are guaranteed
over temperature.
Ordering Information
PACKAGE
CERDIP
TEMPERATURE RANGE
220ns
-55oC to +125oC
HM-6551B/883
300ns
HM1-6551/883
PKG. NO.
F22.4
Pinout
HM-6551/883 (CERDIP)
TOP VIEW
A3 1
A2 2
A1 3
A0 4
A5 5
A6 6
A7 7
GND 8
D0 9
Q0 10
D1 11
22 VCC
21 A4
20 W
19 S1
18 E
17 S2
16 Q3
15 D3
14 Q2
13 D2
12 Q1
PIN DESCRIPTION
A Address Input
E Chip Enable
W Write Enable
S Chip Select
D Data Input
Q Data Output
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-101
File Number 2988.1


HM-6551 Datasheet
Recommendation HM-6551 Datasheet
Part HM-6551
Description 256 x 4 CMOS RAM
Feature HM-6551; HM-6551/883 March 1997 256 x 4 CMOS RAM Description The HM-6551/883 is a 256 x 4 static CMOS RAM fa.
Manufacture Intersil Corporation
Datasheet
Download HM-6551 Datasheet




Intersil Corporation HM-6551
Functional Diagram
HM-6551/883
A0 A
A1 LATCHED
5 GATED
A5
A6
ADDRESS
REGISTER A
ROW
DECODER
32
A7
32 x 32
MATRIX
5
D0
A
8 8 8 8D
Q
Q0
A
D1
A
D2
A
D3
A
GATED COLUMN
DECODER
AND DATA I/O
33
D DATA Q
D
OUTPUT
LATCHES
Q
DQ
L
Q1
A
Q2
A
Q3
A
E
W
L
S2 D SELECT Q
LATCH
S1
AA
LATCHED ADDRESS
REGISTER
A2 A3 A4
NOTES:
1. Select Latch: L Low Q = D and Q latches on rising edge of L.
2. Address Latches And Gated Decoders: Latch on falling edge of E and gate on falling edge of E.
3. All lines positive logic-active high.
4. Three-State Buffers: A high output active.
5. Data Latches: L High Q = D and Q latches on falling edge of L.
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Intersil Corporation HM-6551
HM-6551/883
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance
θJA θJC
CERDIP Package . . . . . . . . . . . . . . . . 60oC/W
15oC/W
Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1930 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V
Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . VCC -2.0V to VCC
Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns Max.
TABLE 1. HM-6551/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
PARAMETER
SYMBOL
(NOTE 1)
CONDITIONS
Output Low Voltage
VOL
VCC = 4.5V
IOL = 1.6mA
Output High Voltage
VOH
VCC = 4.5V
IOH = -0.4mA
Input Leakage Current
II VCC = 5.5V,
VI = GND or VCC
Output Leakage
Current
IOZ VCC = 5.5 V,
VO = GND or VCC
Data Retention Supply
Current
ICCDR
VCC = 2.0V, E = VCC
IO = 0mA,
VI = VCC or GND
Operating Supply
Current
ICCOP
VCC = 5.5V, (Note 2)
E = 1MHz, IO = 0mA
VI = VCC or GND
Standby Supply
Current
ICCSB
VCC = 5.5V,
IO = 0mA
VI = VCC or GND
GROUP A
SUBGROUPS
1, 2, 3
TEMPERATURE
-55oC TA +125oC
LIMITS
MIN MAX
- 0.4
1, 2, 3
-55oC TA +125oC 2.4
-
1, 2, 3
-55oC TA +125oC -1.0
+1.0
1, 2, 3
-55oC TA +125oC -1.0
+1.0
1, 2, 3
-55oC TA +125oC
-
10
1, 2, 3
-55oC TA +125oC
-
4
1, 2, 3
-55oC TA +125oC
-
10
NOTES:
1. All voltages referenced to device GND.
2. Typical derating 1.5mA/MHz increase in ICCOP.
UNITS
V
V
µA
µA
µA
mA
µA
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