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Static RAM. HM-65642 Datasheet

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Static RAM. HM-65642 Datasheet






HM-65642 RAM. Datasheet pdf. Equivalent






HM-65642 RAM. Datasheet pdf. Equivalent


HM-65642

Part

HM-65642

Description

8K x 8 Asynchronous CMOS Static RAM



Feature


HM-65642/883 March 1997 8K x 8 Asynchro nous CMOS Static RAM Description The HM -65642/883 is a CMOS 8192 x 8-bit Stati c Random Access Memory. The pinout is t he JEDEC 28 pin, 8-bit wide standard, w hich allows easy memory board layouts w hich accommodate a variety of industry standard ROM, PROM, EPROM, EEPROM and R AMs. The HM-65642/883 is ideally suited for use in microp.
Manufacture

Intersil Corporation

Datasheet
Download HM-65642 Datasheet


Intersil Corporation HM-65642

HM-65642; rocessor based systems. In particular, i nterfacing with the Intersil 80C86 and 80C88 microprocessors is simplified by the convenient output enable (G) input . The HM-65642/883 is a full CMOS RAM w hich utilizes an array of six transisto r (6T) memory cells for the most stable and lowest possible standby supply cur rent over the full military temperature range. In addition .


Intersil Corporation HM-65642

to this, the high stability of the 6T RA M cell provides excellent protection ag ainst soft errors due to noise and alph a particles. This stability also improv es the radiation tolerance of the RAM o ver that of four transistor or MIX-MOS (4T) devices Features • This Circuit is Processed in Accordance to MIL-STD8 83 and is Fully Conformant Under the Pr ovisions of Paragrap.

Part

HM-65642

Description

8K x 8 Asynchronous CMOS Static RAM



Feature


HM-65642/883 March 1997 8K x 8 Asynchro nous CMOS Static RAM Description The HM -65642/883 is a CMOS 8192 x 8-bit Stati c Random Access Memory. The pinout is t he JEDEC 28 pin, 8-bit wide standard, w hich allows easy memory board layouts w hich accommodate a variety of industry standard ROM, PROM, EPROM, EEPROM and R AMs. The HM-65642/883 is ideally suited for use in microp.
Manufacture

Intersil Corporation

Datasheet
Download HM-65642 Datasheet




 HM-65642
HM-65642/883
March 1997
8K x 8 Asynchronous
CMOS Static RAM
Features
Description
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Full CMOS Design
• Six Transistor Memory Cell
• Low Standby Supply Current . . . . . . . . . . . . . . . .100µA
• Low Operating Supply Current . . . . . . . . . . . . . . . 20mA
• Fast Address Access Time . . . . . . . . . . . . . . . . . . 150ns
• Low Data Retention Supply Voltage. . . . . . . . . . . . 2.0V
• CMOS/TTL Compatible Inputs/Outputs
• JEDEC Approved Pinout
• Equal Cycle and Access Times
• No Clocks or Strobes Required
• Gated Inputs
- No Pull-Up or Pull-Down Resistors Required
• Temperature Range -55oC to +125oC
• Easy Microprocessor Interfacing
• Dual Chip Enable Control
The HM-65642/883 is a CMOS 8192 x 8-bit Static Random
Access Memory. The pinout is the JEDEC 28 pin, 8-bit wide
standard, which allows easy memory board layouts which
accommodate a variety of industry standard ROM, PROM,
EPROM, EEPROM and RAMs. The HM-65642/883 is ideally
suited for use in microprocessor based systems. In particu-
lar, interfacing with the Intersil 80C86 and 80C88 micropro-
cessors is simplified by the convenient output enable (G)
input.
The HM-65642/883 is a full CMOS RAM which utilizes an
array of six transistor (6T) memory cells for the most stable
and lowest possible standby supply current over the full mili-
tary temperature range. In addition to this, the high stability
of the 6T RAM cell provides excellent protection against soft
errors due to noise and alpha particles. This stability also
improves the radiation tolerance of the RAM over that of four
transistor or MIX-MOS (4T) devices
Ordering Information
PACKAGE
CERDIP
CLCC
TEMPERATURE RANGE
150ns/75µA
-55oC to +125oC
HM1-65642B/883
-55oC to +125oC
HM4-65642B/883
150ns/150µA
HM1-65642/883
HM4-65642/883
200ns/250µA
HM1-65642C/883
-
PKG. NO.
F28.6
J32.A
Pinouts
HM-65642/883 (CERDIP)
TOP VIEW
HM4-65642/883 (CLCC)
TOP VIEW
NC 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
DQ0 11
DQ1 12
DQ2 13
GND 14
28 VCC
27 W
26 E2
25 A8
24 A9
23 A11
22 G
21 A10
20 E1
19 DQ7
18 DQ6
17 DQ5
16 DQ4
15 DQ3
4 3 2 1 32 31 30
A6 5
29 A8
A5 6
28 A9
A4 7
27 A11
A3 8
26 NC
A2 9
25 G
A1 10
24 A10
A0 11
23 E1
NC 12
22 DQ7
DQ0 13
21 DQ6
14 15 16 17 18 19 20
PIN
A
DQ
E1
E2
W
G
NC
GND
VCC
DESCRIPTION
Address Input
Data Input/Output
Chip Enable
Chip Enable
Write Enable
Output Enable
No Connections
Ground
Power
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-220
File Number 3004.1




 HM-65642
HM-65642/883
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Input or Output Voltage Applied for all Grades . . . . . . .GND -0.3V to
VCC +0.3V
Typical Derating Factor . . . . . . . . . . . . 5mA/MHz Increase in ICCOP
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical)
θJA
CERDIP Package . . . . . . . . . . . . . . . . 45oC/W
θJC
8oC/W
CLCC Package . . . . . . . . . . . . . . . . . . 55oC/W
10oC/W
Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101,000 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.8V
Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . +2.2V to VCC +0.3V
Data Retention Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 2.0V
Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns Max.
TABLE 1. HM-65642/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
PARAMETER SYMBOL
(NOTE 1)
CONDITIONS
GROUP A
SUBGROUPS TEMPERATURE
LIMITS
MIN MAX UNITS
High Level Output
Voltage
VOH 1 VCC = 4.5V, IO = -1.0mA
1, 2, 3
-55oC TA +125oC 2.4
-
V
Low Level Output
Voltage
High Impedance
Output Leakage
Current
VOL VCC = 4.5V, IO = 4.0mA
IIOZ HM-65642B/883, HM-65642/883
VCC = 5.5V, G = 2.2V,
VI/O = GND or VCC
1, 2, 3
1, 2, 3
-55oC TA +125oC -
0.4
-55oC TA +125oC -1.0 +1.0
V
µA
Input Leakage
Current
Standby Supply
Current
HM-65642C/883
VCC = 5.5V, G = 2.2V,
VI/O = GND or VCC
II HM-65642B/883, HM-65642/883
VCC = 5.5V, VI = GND or VCC
HM-65642C/883
VCC = 5.5V, VI = GND or VCC
ICCSB1
HM-65642B/883
VCC = 5.5V, E1 = VCC -0.3V or
E2 = GND +0.3V
1, 2, 3
-55oC TA +125oC -2.0 +2.0
µA
1, 2, 3
1, 2, 3
1, 2, 3
-55oC TA +125oC -1.0 +1.0
-55oC TA +125oC -2.0 +2.0
-55oC TA +125oC -
100
µA
µA
µA
HM-65642/883
VCC = 5.5V, E1 = VCC -0.3V or
E2 = GND +0.3V
HM-65642C/883
VCC = 5.5V, E1 = VCC -0.3V or
E2 = GND +0.3V
1, 2, 3 -55oC TA +125oC - 250 µA
1, 2, 3 -55oC TA +125oC - 400 µA
Standby Supply
Current
Enable Supply
Current
Operating Supply
Current
ICCSB
ICCEN
ICCOP
VCC = 5.5V, IO = 0mA, E1 = 2.2V or
E2 = 0.8V
VCC = 5.5V, IO = 0mA, E1 =0.8V,
E2 = 2.2V
VCC = 5.5V, G = 5.5V, (Note 2),
f = 1MHz, E1 = 0.8V, E2 = 2.2V
1, 2, 3
1, 2, 3
1, 2, 3
-55oC TA +125oC -
-55oC TA +125oC -
-55oC TA +125oC -
5 mA
5 mA
20 mA
6-221



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