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CMOS RAM. HM1-6504883 Datasheet

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CMOS RAM. HM1-6504883 Datasheet






HM1-6504883 RAM. Datasheet pdf. Equivalent






HM1-6504883 RAM. Datasheet pdf. Equivalent


HM1-6504883

Part

HM1-6504883

Description

4096 x 1 CMOS RAM



Feature


HM-6504/883 March 1997 4096 x 1 CMOS RA M Description The HM-6504/883 is a 4096 x 1 static CMOS RAM fabricated using s elf-aligned silicon gate technology. Th e device utilizes synchronous circuitry to achieve high performance and low po wer operation. On-chip latches are prov ided for addresses, data input and data output allowing efficient interfacing with microprocessor.
Manufacture

Intersil Corporation

Datasheet
Download HM1-6504883 Datasheet


Intersil Corporation HM1-6504883

HM1-6504883; systems. The data output can be forced to a high impedance state for use in ex panded memory arrays. Gated inputs allo w lower operating current and also elim inate the need for pull up or pull down resistors. The HM-6504/883 is a fully static RAM and may be maintained in any state for an indefinite period of tim e. Data retention supply voltage and su pply current are gua.


Intersil Corporation HM1-6504883

ranteed over temperature. Features • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1 . • Low Power Standby . . . . . . . . . . . . . . . . . . . 125µW Max • L ow Power Operation . . . . . . . . . . . . . 35mW/MHz Max • Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min • TTL Com.

Part

HM1-6504883

Description

4096 x 1 CMOS RAM



Feature


HM-6504/883 March 1997 4096 x 1 CMOS RA M Description The HM-6504/883 is a 4096 x 1 static CMOS RAM fabricated using s elf-aligned silicon gate technology. Th e device utilizes synchronous circuitry to achieve high performance and low po wer operation. On-chip latches are prov ided for addresses, data input and data output allowing efficient interfacing with microprocessor.
Manufacture

Intersil Corporation

Datasheet
Download HM1-6504883 Datasheet




 HM1-6504883
HM-6504/883
March 1997
4096 x 1 CMOS RAM
Features
Description
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Low Power Standby . . . . . . . . . . . . . . . . . . . 125µW Max
• Low Power Operation . . . . . . . . . . . . . 35mW/MHz Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min
• TTL Compatible Input/Output
• Three-State Output
• Standard JEDEC Pinout
• Fast Access Time. . . . . . . . . . . . . . . . . . 120/200ns Max
• 18 Pin Package for High Density
• On-Chip Address Register
The HM-6504/883 is a 4096 x 1 static CMOS RAM
fabricated using self-aligned silicon gate technology. The
device utilizes synchronous circuitry to achieve high perfor-
mance and low power operation.
On-chip latches are provided for addresses, data input and
data output allowing efficient interfacing with microprocessor
systems. The data output can be forced to a high impedance
state for use in expanded memory arrays.
Gated inputs allow lower operating current and also elimi-
nate the need for pull up or pull down resistors. The
HM-6504/883 is a fully static RAM and may be maintained in
any state for an indefinite period of time.
Data retention supply voltage and supply current are guaran-
teed over temperature.
• Gated Inputs - No Pull Up or Pull Down Resistors
Required
Ordering Information
PACKAGE TEMPERATURE RANGE
200ns
CERDIP
-55oC to +125oC
HM1-6504B/883
300ns
HM1-6504/883
PKG. NO
F18.3
Pinout
HM-6504/883 (CERDIP)
TOP VIEW
A0 1
A1 2
A2 3
A3 4
A4 5
A5 6
Q7
W8
GND 9
18 VCC
17 A6
16 A7
15 A8
14 A9
13 A10
12 A11
11 D
10 E
PIN DESCRIPTION
A Address Input
E Chip Enable
W Write Enable
D Data Input
Q Data Output
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-134
File Number 2993.1




 HM1-6504883
Functional Diagram
HM-6504/883
LSB
A8
A7
A6
A0
A1
A2
D
W
E
LATCHED
ADDRESS
REGISTER
L
A
6
A
6
GATED
ROW
DECODER
G
D LATCH Q
DQ
LATCH
L
L
L
DQ
LATCH
64 x 64
64 MATRIX
64
G
GATED COLUMN D
Q
A
DECODER AND
DATA I/O
LATCH
L
66
AA
L LATCHED
ADDRESS
REGISTER
Q
A
LSB A11 A5 A4 A3 A9 A10
NOTES:
1. All lines active high-positive logic.
2. Three-state Buffers: A high output active.
3. Control and Data Latches: L low Q = D and Q latches on rising edge of L.
4. Address Latches: Latch on falling edge of E.
5. Gated Decoders: Gate on rising edge of G.
6-135



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