CMOS RAM. HM1-6561B883 Datasheet

HM1-6561B883 RAM. Datasheet pdf. Equivalent


Intersil Corporation HM1-6561B883
HM-6561/883
March 1997
256 x 4 CMOS RAM
Features
Description
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Low Power Standby . . . . . . . . . . . . . . . . . . . . 50µW Max
• Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max
• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 200ns Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min
• TTL Compatible Input/Output
• High Output Drive - 1 TTL Load
• On-Chip Address Registers
• Common Data In/Out
The HM-6561/883 is a 256 x 4 static CMOS RAM fabricated
using self-aligned silicon gate technology. Synchronous
circuit design techniques are employed to achieve high per-
formance and low power operation.
On-chip latches are provided for address and data outputs
allowing efficient interfacing with microprocessor systems.
The data output buffers can be forced to a high impedance
state for use in expanded memory arrays. The data inputs
and outputs are multiplexed internally for common I/O bus
compatibility.
The HM-6561/883 is a fully static RAM and may be
maintained in any state for an indefinite period of time. Data
retention supply voltage and supply current are guaranteed
over temperature.
• Three-State Output
• Easy Microprocessor Interfacing
Ordering Information
PACKAGE TEMPERATURE RANGE
220ns
CERDIP
-55oC to +125oC
HM1-6561B/883
300ns
HM1-6561/883
PKG. NO.
F18.3
Pinout
HM-6561/883 (CERDIP)
TOP VIEW
A3 1
A2 2
A1 3
A0 4
A5 5
A6 6
A7 7
GND 8
E9
18 VCC
17 A4
16 W
15 S1
14 DQ3
13 DQ2
12 DQ1
11 DQ0
10 S2
PIN DESCRIPTION
A Address Input
E Chip Enable
W Write Enable
S Chip Select
DQ Data In/Out
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-117
File Number 2990.1


HM1-6561B883 Datasheet
Recommendation HM1-6561B883 Datasheet
Part HM1-6561B883
Description 256 x 4 CMOS RAM
Feature HM1-6561B883; HM-6561/883 March 1997 256 x 4 CMOS RAM Description The HM-6561/883 is a 256 x 4 static CMOS RAM fa.
Manufacture Intersil Corporation
Datasheet
Download HM1-6561B883 Datasheet




Intersil Corporation HM1-6561B883
Functional Diagram
HM-6561/883
A0
A1
A5
A6
A7
DQ0
DQ1
DQ2
DQ3
W
E
S1
S2
LATCHED
ADDRESS
REGISTER
A
A
L
5
5
A Q LATCH
LATCH
AQ
A Q LATCH
A Q LATCH
GATED
ROW
DECODER
G
A
D
LA
D
LA
D
LA
D
L
32 x 32
32 MATRIX
8888
G
GATED COLUMN
DECODER
AND DATA I / O
3
A
3
A
L LATCHED ADDRESS
REGISTER
A2 A3 A4
NOTES:
1. All lines positive logic-active high.
2. Three-state Buffers: A high output active.
3. Data Latches: L high Q = D and Q latches on falling edge of L.
4. Address Latches and Gated Decoders: Latch on falling edge of E and gate on falling edge of E.
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Intersil Corporation HM1-6561B883
HM-6561/883
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Input or Output Voltage. . . . . . . . . . . . . . . GND -0.3V to VCC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance
θJA θJC
CERDIP Package . . . . . . . . . . . . . . . . 74oC/W
18oC/W
Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1944 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V
Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . VCC - 2.0V to VCC
Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns Max
TABLE 1. HM-6561/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
PARAMETER
SYMBOL
(NOTE 1)
CONDITIONS
GROUP A
SUBGROUPS
TEMPERATURE
LIMITS
MIN MAX UNITS
Output Low Voltage
VOL
VCC = 4.5V,
IOL = 1.6mA
1, 2, 3
-55oC TA +125oC
-
0.4
V
Output High Voltage
VOH
VCC = 4.5V,
IOH = -0.4mA
1, 2, 3
-55oC TA +125oC 2.4
-
V
Input Leakage Current
II VCC = 5.5V,
1, 2, 3
-55oC TA +125oC -1.0 +1.0
µA
VI = GND or VCC
Input/Output Leakage Current
IIOZ VCC = 5.5V,
VIO = GND or
VCC
1, 2, 3
-55oC TA +125oC -1.0 +1.0
µA
Data Retention Supply Current
ICCDR
VCC = 2.0V,
E = VCC,
IO = 0mA,
1, 2, 3
-55oC TA +125oC
-
10
µA
Operating Supply Current
ICCOP
VCC = 5.5V,
(Note 2),
E = 1MHz,
W = GND,
VI = VCC or GND
1, 2, 3
-55oC TA +125oC
-
4
mA
Standby Supply Current
ICCSB
VCC = 5.5V,
IO = 0mA,
VI = VCC or GND
1, 2, 3
-55oC TA +125oC
-
10
µA
NOTES:
1. All voltages referenced to device GND.
2. Typical derating 1.5mA/MHz increase in ICCOP.
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