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HM3-6514-9 Dataheets PDF



Part Number HM3-6514-9
Manufacturers Intersil Corporation
Logo Intersil Corporation
Description 1024 x 4 CMOS RAM
Datasheet HM3-6514-9 DatasheetHM3-6514-9 Datasheet (PDF)

HM-6514 March 1997 1024 x 4 CMOS RAM Description The HM-6514 is a 1024 x 4 static CMOS RAM fabricated using self-aligned silicon gate technology. The device utilizes synchronous circuitry to achieve high performance and low power operation. On-chip latches are provided for addresses allowing efficient interfacing with microprocessor systems. The data output can be forced to a high impedance state for use in expanded memory arrays. Gated inputs allow lower operating current and also eliminate the.

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HM-6514 March 1997 1024 x 4 CMOS RAM Description The HM-6514 is a 1024 x 4 static CMOS RAM fabricated using self-aligned silicon gate technology. The device utilizes synchronous circuitry to achieve high performance and low power operation. On-chip latches are provided for addresses allowing efficient interfacing with microprocessor systems. The data output can be forced to a high impedance state for use in expanded memory arrays. Gated inputs allow lower operating current and also eliminate the need for pull up or pull down resistors. The HM-6514 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaranteed over temperature. Features • Low Power Standby . . . . . . . . . . . . . . . . . . . 125µW Max • Low Power Operation . . . . . . . . . . . . . 35mW/MHz Max • Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min • TTL Compatible Input/Output • Common Data Input/Output • Three-State Output • Standard JEDEC Pinout • Fast Access Time. . . . . . . . . . . . . . . . . . 120/200ns Max • 18 Pin Package for High Density • On-Chip Address Register • Gated Inputs - No Pull Up or Pull Down Resistors Required Ordering Information 120ns HM3-6514S-9 HM1-6514S-9 24502BVA 8102402VA 200ns HM3-6514B-9 HM1-6514B-9 8102404VA 300ns HM3-6514-9 HM1-6514-9 8102406VA HM4-6514-B TEMPERATURE RANGE -40oC to +85oC -40oC to +85oC -40oC to +85oC -55oC to +125oC PACKAGE PDIP CERDIP JAN# SMD# CLCC PKG. NO. E18.3 F18.3 F18.3 F18.3 J18.B J18.B Pinouts HM-6514 (PDIP, CERDIP) TOP VIEW A6 A5 A4 A3 A0 A1 A2 E GND 1 2 3 4 5 6 7 8 9 18 VCC 17 A7 16 A8 15 A9 14 DQ0 13 DQ1 12 DQ2 11 DQ3 10 W HM-6514 (CLCC) TOP VIEW A6 VCC 18 A5 PIN A E W D Q DESCRIPTION Address Input Chip Enable Write Enable A0 5 6 7 A4 A3 3 4 2 1 17 16 A8 15 A9 14 DQ0 13 DQ1 12 DQ2 Data Input Data Output A1 A2 8 E 9 GND 10 W 11 DQ3 A7 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 File Number 2995.1 6-1 HM-6514 Functional Diagram LSB A9 A8 A7 A6 A5 A4 A LATCHED ADDRESS REGISTER 6 A 6 L G L 16 16 16 16 GATED COLUMN I/O SELECT G GATED ROW DECODER 64 x 64 MATRIX 64 LSB A2 A1 A0 A3 A LATCHED ADDRESS REGISTER 4 A 4 4 1 OF 4 E W DQ 6-2 HM-6514 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Information Thermal Resistance (Typical) θJA θJC CERDIP Package . . . . . . . . . . . . . . . . 75oC/W 15oC/W PDIP Package . . . . . . . . . . . . . . . . . . . 75oC/W N/A CLCC Package . . . . . . . . . . . . . . . . . . 90oC/W 33oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperat.


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