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CMOS RAM. HM3-6514-9 Datasheet |
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HM-6514
March 1997
1024 x 4 CMOS RAM
Features
Description
• Low Power Standby . . . . . . . . . . . . . . . . . . . 125µW Max
• Low Power Operation . . . . . . . . . . . . . 35mW/MHz Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min
The HM-6514 is a 1024 x 4 static CMOS RAM fabricated
using self-aligned silicon gate technology. The device utilizes
synchronous circuitry to achieve high performance and low
power operation.
• TTL Compatible Input/Output
• Common Data Input/Output
• Three-State Output
• Standard JEDEC Pinout
• Fast Access Time. . . . . . . . . . . . . . . . . . 120/200ns Max
• 18 Pin Package for High Density
• On-Chip Address Register
• Gated Inputs - No Pull Up or Pull Down Resistors
Required
On-chip latches are provided for addresses allowing efficient
interfacing with microprocessor systems. The data output
can be forced to a high impedance state for use in expanded
memory arrays.
Gated inputs allow lower operating current and also elimi-
nate the need for pull up or pull down resistors. The
HM-6514 is a fully static RAM and may be maintained in any
state for an indefinite period of time.
Data retention supply voltage and supply current are guaran-
teed over temperature.
Ordering Information
120ns
HM3-6514S-9
HM1-6514S-9
24502BVA
8102402VA
-
-
200ns
HM3-6514B-9
HM1-6514B-9
-
8102404VA
-
-
300ns
HM3-6514-9
HM1-6514-9
-
8102406VA
-
HM4-6514-B
TEMPERATURE RANGE
-40oC to +85oC
-40oC to +85oC
-
-
-40oC to +85oC
-55oC to +125oC
PACKAGE
PDIP
CERDIP
JAN#
SMD#
CLCC
PKG. NO.
E18.3
F18.3
F18.3
F18.3
J18.B
J18.B
Pinouts
HM-6514 (PDIP, CERDIP)
TOP VIEW
A6 1
A5 2
A4 3
A3 4
A0 5
A1 6
A2 7
E8
GND 9
18 VCC
17 A7
16 A8
15 A9
14 DQ0
13 DQ1
12 DQ2
11 DQ3
10 W
PIN DESCRIPTION
A Address Input
E Chip Enable
W Write Enable
D Data Input
Q Data Output
HM-6514 (CLCC)
TOP VIEW
2 1 18 17
A4 3
16 A8
A3 4
15 A9
A0 5
14 DQ0
A1 6
13 DQ1
A2 7
12 DQ2
8 9 10 11
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-1
File Number 2995.1
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Functional Diagram
HM-6514
LSB A9
A8
A7
A6
A5
A4
LSB A2
A1
A0
A3
E
W
LATCHED
ADDRESS
REGISTER
A
6
A
6
L
L
LATCHED
ADDRESS
REGISTER
A
4
A
4
GATED
ROW
DECODER
G
64 x 64
64 MATRIX
16 16 16 16
GATED
COLUMN
I/O SELECT
G
4
1 OF 4
DQ
6-2
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HM-6514
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Ranges:
HM-6514S-9, HM-6514B-9, HM-6514-9 . . . . . . . . -40oC to +85oC
HM-6514B-8, HM-6514-8 . . . . . . . . . . . . . . . . . . -55oC to +125oC
Thermal Information
Thermal Resistance (Typical)
θJA θJC
CERDIP Package . . . . . . . . . . . . . . . . 75oC/W
15oC/W
PDIP Package . . . . . . . . . . . . . . . . . . . 75oC/W
N/A
CLCC Package . . . . . . . . . . . . . . . . . . 90oC/W
33oC/W
Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC
Maximum Junction Temperature
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6910 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications VCC = 5V ±10%; TA = -40oC to +85oC (HM-6514S-9, HM-6514B-9, HM-6514-9)
TA = -55oC to +125oC (HM-6514B-8, HM-6514-8)
LIMITS
SYMBOL
PARAMETER
MIN
MAX
UNITS
TEST CONDITIONS
ICCSB
Standby Supply Current
HM-6514-9
HM-6514-8
-
-
25 µA IO = 0mA, E = VCC -0.3V, VCC = 5.5V
50 µA
ICCOP Operating Supply Current (Note 1)
ICCDR
Data Retention Supply
Current
HM-6514-9
HM-6514-8
-
-
-
7 mA E = 1MHz, IO = 0mA, VI = GND,
VCC = 5.5V
15 µA IO = 0mA, VCC = 2.0V, E = VCC
25 µA
VCCDR Data Retention Supply Voltage
2.0 -
V
II
IIOZ
VIL
VIH
VOL
VOH1
VOH2
Input Leakage Current
Input/Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output High Voltage (Note 2)
-1.0 +1.0
-1.0 +1.0
-0.3 0.8
VCC -2.0
-
VCC +0.3
0.4
2.4 -
VCC -0.4
-
µA VI = VCC or GND, VCC = 5.5V
µA VIO = VCC or GND, VCC = 5.5V
V VCC = 4.5V
V VCC = 5.5V
V IO = 2.0mA, VCC = 4.5V
V IO = -1.0mA, VCC = 4.5V
V IO = -100µA, VCC = 4.5V
Capacitance TA = +25oC
SYMBOL
PARAMETER
CI Input Capacitance (Note 2)
CIO Input/Output Capacitance (Note 2)
NOTES:
1. Typical derating 5mA/MHz increase in ICCOP.
2. Tested at initial design and after major design changes.
MAX
8
10
UNITS
pF
pF
TEST CONDITIONS
f = 1MHz, All measurements are
referenced to device GND
6-3
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