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HM5212325FBPC-B60 Dataheets PDF



Part Number HM5212325FBPC-B60
Manufacturers Hitachi Semiconductor
Logo Hitachi Semiconductor
Description 128M LVTTL interface SDRAM 100 MHz 1-Mword x 32-bit x 4-bank PC/100 SDRAM
Datasheet HM5212325FBPC-B60 DatasheetHM5212325FBPC-B60 Datasheet (PDF)

HM5212325FBPC-B60 128M LVTTL interface SDRAM 100 MHz 1-Mword × 32-bit × 4-bank PC/100 SDRAM ADE-203-1122C (Z) Rev. 1.0 May. 12 , 2000 Description The Hitachi HM5212325FBPC is a 128-Mbit SDRAM organized as 1048576-word × 32-bit × 4-bank. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 90-bump fine pitch BGA. Features • • • • • • • • • Single chip wide bit solution (× 32) 3.3 V power supply Clock frequency: 100 MHz (max) LVTTL interface Extre.

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HM5212325FBPC-B60 128M LVTTL interface SDRAM 100 MHz 1-Mword × 32-bit × 4-bank PC/100 SDRAM ADE-203-1122C (Z) Rev. 1.0 May. 12 , 2000 Description The Hitachi HM5212325FBPC is a 128-Mbit SDRAM organized as 1048576-word × 32-bit × 4-bank. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 90-bump fine pitch BGA. Features • • • • • • • • • Single chip wide bit solution (× 32) 3.3 V power supply Clock frequency: 100 MHz (max) LVTTL interface Extremely small foot print: 0.8 mm pitch  Package: FBGA (BP-90) 4 banks can operate simultaneously and independently Burst read/write operation and burst read/single write operation capability Programmable burst length: 4/8/full page 2 variations of burst sequence  Sequential (BL = 4/8/full page)  Interleave (BL = 4/8) Programmable CAS latency: 2/3 Byte control by DQMB Refresh cycles: 4096 refresh cycles/64 ms • • • HM5212325FBPC-B60 • 2 variations of refresh  Auto refresh  Self refresh • Full page burst length capability  Sequential burst  Burst stop capability Ordering Information Type No. HM5212325FBPC-B60* Frequency 100 MHz CAS latency 3 Package 10 mm × 13 mm 90 bump FBGA (BP-90) Note: 66 MHz operation at CAS latency = 2. 2 HM5212325FBPC-B60 Pin Arrangement 90-bump FBGA 1 A B C D E F G H J K L M N P Q VSS 2 DQ15 3 VSS 6 VCC 7 DQ0 8 VCC DQ14 DQ13 VCC VSS DQ2 DQ1 DQ12 DQ11 VSS VCC DQ4 DQ3 DQ10 DQ9 VCC VSS DQ6 DQ5 DQ8 DQ MB1 NC NC VSS VCC NC DQ7 DQ MB0 RAS Open NC CAS WE CKE CLK NC CS A11 A9 A8 A12 NC NC A5 DQ MB3 DQ31 A6 A7 A13 A10 A0 DQ MB2 DQ16 A3 A4 A1 A2 NC VSS VCC NC DQ29 DQ30 VCC VSS DQ17 DQ18 DQ27 DQ28 VSS VCC DQ19 DQ20 DQ25 DQ26 VCC VSS DQ21 DQ22 VSS DQ24 VSS VCC DQ23 VCC (Top view) 3 HM5212325FBPC-B60 Pin Description Pin name A0 to A13 Function Address input Row address Column address A0 to A11 A0 to A7 Bank select address A12/A13 (BS) DQ0 to DQ31 CS RAS CAS WE DQMB0 to DQMB3 CLK CKE VCC VSS Open Note: Data-input/output Chip select Row address strobe command Column address strobe command Write enable Byte data mask* 1 Clock input Clock enable Power supply Ground Open* 2 1. DQMB0: DQ0 to DQ7 DQMB1: DQ8 to DQ15 DQMB2: DQ16 to DQ23 DQMB3: DQ24 to DQ31 2. Don’t connect. Internally connected with die. 4 HM5212325FBPC-B60 Block Diagram 14 A0 to A13 CS RAS CAS WE CLK CKE 64-Mbit SDRAM 4M × 16 64-Mbit SDRAM 4M × 16 4 DQMB 0 to DQMB 3 32 DQ 0 to DQ 31 2 16 2 16 Power-up Sequence and Initialization Sequence Power up sequence 100 µs VCC CKE, DQMB CLK CS, DQ 0V Low Low Low Power stabilize Initialization sequence 200 µs 5 HM5212325FBPC-B60 Absolute Maximum Ratings Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Operating temperature Storage temperature Note: 1. Respect to V SS . Symbol VT VCC Iout Topr Tstg Value –0.5 to VCC + 0.5 (≤ 4.6 (max)) –0.5 to +4.6 50 0 to +70 (Tj max = 110) –55 to +125.


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