HM5225805B-75

HM5225165B-75/A6/B6 HM5225805B-75/A6/B6 HM5225405B-75/A6/B6 256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword × 16-bit × 4-bank/8-Mword × 8-bit × 4-bank /16-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAM E0082H10 (1st edition) (Previous ADE-203-1073B (Z)) Jan. 31, 2001 Description The HM5225165B is a 256-Mbit SDRAM organized as 4194304-word × 16-bit × 4 bank. The HM5225805B is a 256-Mbit SDRAM organized as 8388608-word × 8-bit × 4 bank. The HM5225405B is a 256-Mbit SDRAM organized as 16777216-word × 4-bit × 4 bank. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II. Features 3.3 V power supply Clock frequency: 133 MHz/100 MHz (max) LVTTL interface Single pulsed RAS 4 banks can operate simultaneously and independently Burst read/write operation and burst read/single write operation capability Programmable burst length: 1/2/4/8 2 variations of burst sequence  Sequential (BL = 1/2/4/8)  Interleave (BL = 1/2/4/8) Programmable CAS latency: 2/3 Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. HM5225165B/HM5225805B/HM5225405B-75/A6/B6 Byte control by DQM : DQM (HM5225805B/HM5225405B) : DQMU/DQML (HM5225165B) Refresh cycles: 8192 refresh cycles/64 ms 2 variations of refresh  Auto refresh  Self refresh Ordering Information Type No. HM5225165BTT-75* HM5225165BTT-A6 HM5225165BTT-B6* 2 HM5225165BLTT-75* 1 HM5225165BLTT-A6 HM5225165BLTT-B6* 2 HM5...