PC/100 SDRAM. HM5259165B-75 Datasheet

HM5259165B-75 SDRAM. Datasheet pdf. Equivalent

HM5259165B-75 Datasheet
Recommendation HM5259165B-75 Datasheet
Part HM5259165B-75
Description 512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword 16-bit 4-bank/16-Mword 8-bit 4-bank /32-Mword 4-bit 4-bank PC/133/ PC/100 SDRAM
Feature HM5259165B-75; HM5259165B-75/A6 HM5259805B-75/A6 HM5259405B-75/A6 512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mwor.
Manufacture Elpida Memory
Datasheet
Download HM5259165B-75 Datasheet




Elpida Memory HM5259165B-75
HM5259165B-75/A6
HM5259805B-75/A6
HM5259405B-75/A6
512M LVTTL interface SDRAM
133 MHz/100 MHz
8-Mword × 16-bit × 4-bank/16-Mword × 8-bit × 4-bank
/32-Mword × 4-bit × 4-bank
PC/133, PC/100 SDRAM
E0118H10
Ver. 1.0
Apr. 6, 2001
Description
The HM5259165B is a 512-Mbit SDRAM organized as 8388608-word × 16-bit × 4 bank. The HM5259805B
is a 512-Mbit SDRAM organized as 16777216-word × 8-bit × 4 bank. The HM5259405B is a 512-Mbit
SDRAM organized as 33554432-word × 4-bit × 4 bank. All inputs and outputs are referred to the rising edge
of the clock input. It is packaged in standard 54-pin plastic TSOP II.
Features
3.3 V power supply
Clock frequency: 133 MHz/100 MHz (max)
LVTTL interface
Single pulsed RAS
4 banks can operate simultaneously and independently
Burst read/write operation and burst read/single write operation capability
Programmable burst length: 1/2/4/8
2 variations of burst sequence
Sequential (BL = 1/2/4/8)
Interleave (BL = 1/2/4/8)
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.



Elpida Memory HM5259165B-75
HM5259165B/HM5259805B/HM5259405B-75/A6
Programmable CAS latency: 2/3
Byte control by DQM : DQM (HM5259805B/HM5259405B)
: DQMU/DQML (HM5259165B)
Refresh cycles: 8192 refresh cycles/32 ms
2 variations of refresh
Auto refresh
Self refresh
Ordering Information
Type No.
Frequency
CAS latency
HM5259165BTD-75*1
HM5259165BTD-A6
133 MHz
100 MHz
3
2/3
HM5259805BTD-75*1
HM5259805BTD-A6
133 MHz
100 MHz
3
2/3
HM5259405BTD-75*1
133 MHz
3
HM5259405BTD-A6
100 MHz
2/3
Notes: 1. 100 MHz operation at CAS latency = 2
Package
400-mil 54-pin plastic TSOP II (TTP-54DA)
Data Sheet E0118H10
2



Elpida Memory HM5259165B-75
HM5259165B/HM5259805B/HM5259405B-75/A6
Pin Arrangement (HM5259165B)
VCC
DQ0
VCCQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VCCQ
DQ5
DQ6
VSSQ
DQ7
VCC
DQML
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
VCC
54-pin TSOP
1 54
2 53
3 52
4 51
5 50
6 49
7 48
8 47
9 46
10 45
11 44
12 43
13 42
14 41
15 40
16 39
17 38
18 37
19 36
20 35
21 34
22 33
23 32
24 31
25 30
26 29
27 28
(Top view)
VSS
DQ15
VSSQ
DQ14
DQ13
VCCQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VCCQ
DQ8
VSS
NC
DQMU
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
Pin Description
Pin name
A0 to A12,
BA0, BA1
Function
Address input
Pin name
WE
Function
Write enable
Row address
A0 to A12
DQMU/DQML Input/output mask
Column address A0 to A9
CLK
Clock input
Bank select address BA0/BA1 (BS) CKE
Clock enable
DQ0 to DQ15
CS
RAS
CAS
Data-input/output
Chip select
Row address strobe command
Column address strobe command
VCC
VSS
VCCQ
VSSQ
NC
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Data Sheet E0118H10
3







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