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HM5259805B-75 Dataheets PDF



Part Number HM5259805B-75
Manufacturers Elpida Memory
Logo Elpida Memory
Description 512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword 16-bit 4-bank/16-Mword 8-bit 4-bank /32-Mword 4-bit 4-bank PC/133/ PC/100 SDRAM
Datasheet HM5259805B-75 DatasheetHM5259805B-75 Datasheet (PDF)

HM5259165B-75/A6 HM5259805B-75/A6 HM5259405B-75/A6 512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword × 16-bit × 4-bank/16-Mword × 8-bit × 4-bank /32-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAM E0118H10 Ver. 1.0 Apr. 6, 2001 Description The HM5259165B is a 512-Mbit SDRAM organized as 8388608-word × 16-bit × 4 bank. The HM5259805B is a 512-Mbit SDRAM organized as 16777216-word × 8-bit × 4 bank. The HM5259405B is a 512-Mbit SDRAM organized as 33554432-word × 4-bit × 4 bank. All inputs and outputs.

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HM5259165B-75/A6 HM5259805B-75/A6 HM5259405B-75/A6 512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword × 16-bit × 4-bank/16-Mword × 8-bit × 4-bank /32-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAM E0118H10 Ver. 1.0 Apr. 6, 2001 Description The HM5259165B is a 512-Mbit SDRAM organized as 8388608-word × 16-bit × 4 bank. The HM5259805B is a 512-Mbit SDRAM organized as 16777216-word × 8-bit × 4 bank. The HM5259405B is a 512-Mbit SDRAM organized as 33554432-word × 4-bit × 4 bank. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II. Features • • • • • • • • 3.3 V power supply Clock frequency: 133 MHz/100 MHz (max) LVTTL interface Single pulsed RAS 4 banks can operate simultaneously and independently Burst read/write operation and burst read/single write operation capability Programmable burst length: 1/2/4/8 2 variations of burst sequence  Sequential (BL = 1/2/4/8)  Interleave (BL = 1/2/4/8) Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. HM5259165B/HM5259805B/HM5259405B-75/A6 • Programmable CAS latency: 2/3 • Byte control by DQM : DQM (HM5259805B/HM5259405B) : DQMU/DQML (HM5259165B) • Refresh cycles: 8192 refresh cycles/32 ms • 2 variations of refresh  Auto refresh  Self refresh Ordering Information Type No. HM5259165BTD-75* HM5259165BTD-A6 1 Frequency 133 MHz 100 MHz 133 MHz 100 MHz 133 MHz 100 MHz CAS latency 3 2/3 3 2/3 3 2/3 Package 400-mil 54-pin plastic TSOP II (TTP-54DA) HM5259805BTD-75* 1 HM5259805BTD-A6 HM5259405BTD-75* 1 HM5259405BTD-A6 Notes: 1. 100 MHz operation at CAS latency = 2 Data Sheet E0118H10 2 HM5259165B/HM5259805B/HM5259405B-75/A6 Pin Arrangement (HM5259165B) 54-pin TSOP VCC DQ0 VCCQ DQ1 DQ2 VSSQ DQ3 DQ4 VCCQ DQ5 DQ6 VSSQ DQ7 VCC DQML WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 (Top view) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ15 VSSQ DQ14 DQ13 VCCQ DQ12 DQ11 VSSQ DQ10 DQ9 VCCQ DQ8 VSS NC DQMU CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS Pin Description Pin name A0 to A12, BA0, BA1 Function Address input  Row address  Column address DQ0 to DQ15 CS RAS CAS Data-input/output Chip select Row address strobe command Column address strobe command A0 to A12 A0 to A9 Pin name WE Function Write enable DQMU/DQML Input/output mask CLK CKE VCC VSS VCCQ VSS Q NC Clock input Clock enable Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit No connection  Bank select address BA0/BA1 (BS) Data Sheet E0118H10 3 HM5259165B/HM5259805B/HM5259405B-75/A6 Pin Arrangement (HM5259805B) 54-pin TSOP VCC DQ0 VCCQ NC DQ1 VSSQ NC DQ2 VCCQ NC DQ3 VSSQ NC VCC NC WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 (Top view) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ7 VSSQ NC DQ6 VCCQ NC DQ5 VSSQ NC DQ4 VCCQ NC VSS NC DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS Pin Description Pin name A0 to A12, BA0, BA1 Function Address input  Row address  Column address DQ0 to DQ7 CS RAS CAS Data-input/output Chip select Row address strobe command Column address strobe command A0 to A12 A0 to A9, A11 Pin name WE DQM CLK CKE VCC VSS VCCQ VSS Q NC Function Write enable Input/output mask Clock input Clock enable Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit No connection  Bank select address BA0/BA1 (BS) Data Sheet E0118H10 4 HM5259165B/HM5259805B/HM5259405B-75/A6 Pin Arrangement (HM5259405B) 54-pin TSOP VCC NC VCCQ NC DQ0 VSSQ NC NC VCCQ NC DQ1 VSSQ NC VCC NC WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 (Top view) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS NC VSSQ NC DQ3 VCCQ NC NC VSSQ NC DQ2 VCCQ NC VSS NC DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS Pin Description Pin name A0 to A12, BA0, BA1 Function Address input  Row address  Column address DQ0 to DQ3 CS RAS CAS Data-input/output Chip select Row address strobe command Column address strobe command A0 to A12 Pin name WE DQM Function Write enable Input/output mask Clock input Clock enable Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit No connection A0 to A9, A11 A12 CLK CKE VCC VSS VCCQ VSS Q NC  Bank select address BA0/BA1 (BS) Data Sheet E0118H10 5 HM5259165B/HM5259805B/HM5259405B-75/A6 Block Diagram (HM5259165B) A0 to A12, BA0, BA1 Upper pellet A0 to A9 Column address counter Column address buffer A0 to A12, BA0, BA1 Row address buffer Refresh counter Row decoder Sense amplifier & I/O bus Sense amplifier & I/O bus Row decoder Sense amplifier & I/O bus Row decoder Sense amplifier & I/O bus Row decoder Memory array Column decoder Bank0 8192 row × 1024 column × 8 bi.


HM5259405B-A6 HM5259805B-75 HM5259805B-A6


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