MHz/100 MHz. HM5264805F-B60 Datasheet

HM5264805F-B60 MHz. Datasheet pdf. Equivalent

HM5264805F-B60 Datasheet
Recommendation HM5264805F-B60 Datasheet
Part HM5264805F-B60
Description 64M LVTTL interface SDRAM 133 MHz/100 MHz
Feature HM5264805F-B60; HM5264165F-75/A60/B60 HM5264805F-75/A60/B60 HM5264405F-75/A60/B60 64M LVTTL interface SDRAM 133 MHz/.
Manufacture Hitachi Semiconductor
Datasheet
Download HM5264805F-B60 Datasheet




Hitachi Semiconductor HM5264805F-B60
HM5264165F-75/A60/B60
HM5264805F-75/A60/B60
HM5264405F-75/A60/B60
64M LVTTL interface SDRAM
133 MHz/100 MHz
1-Mword × 16-bit × 4-bank/2-Mword × 8-bit × 4-bank
/4-Mword × 4-bit × 4-bank
PC/133, PC/100 SDRAM
ADE-203-940B (Z)
Rev. 1.0
Nov. 10, 1999
Description
The Hitachi HM5264165F is a 64-Mbit SDRAM organized as 1048576-word × 16-bit × 4 bank. The Hitachi
HM5264805F is a 64-Mbit SDRAM organized as 2097152-word × 8-bit × 4 bank. The Hitachi HM5264405F
is a 64-Mbit SDRAM organized as 4194304-word × 4-bit × 4 bank. All inputs and outputs are referred to the
rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.
Features
3.3 V power supply
Clock frequency: 133 MHz/100 MHz (max)
LVTTL interface
Single pulsed RAS
4 banks can operate simultaneously and independently
Burst read/write operation and burst read/single write operation capability
Programmable burst length: 1/2/4/8/full page
2 variations of burst sequence
Sequential (BL = 1/2/4/8/full page)
Interleave (BL = 1/2/4/8)



Hitachi Semiconductor HM5264805F-B60
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
Programmable CAS latency: 2/3
Byte control by DQM: DQM (HM5264805F/HM5264405F)
DQMU/DQML (HM5264165F)
Refresh cycles: 4096 refresh cycles/64 ms
2 variations of refresh
Auto refresh
Self refresh
Full page burst length capability
Sequential burst
Burst stop capability
Ordering Information
Type No.
Frequency
CAS latency
HM5264165FTT-75*1
HM5264165FTT-A60
HM5264165FTT-B60*2
133 MHz
100 MHz
100 MHz
3
2/3
3
HM5264165FLTT-75*1
HM5264165FLTT-A60
HM5264165FLTT-B60*2
133 MHz
100 MHz
100 MHz
3
2/3
3
HM5264805FTT-75*1
HM5264805FTT-A60
HM5264805FTT-B60*2
133 MHz
100 MHz
100 MHz
3
2/3
3
HM5264805FLTT-75*1
HM5264805FLTT-A60
HM5264805FLTT-B60*2
133 MHz
100 MHz
100 MHz
3
2/3
3
HM5264405FTT-75*1
HM5264405FTT-A60
HM5264405FTT-B60*2
133 MHz
100 MHz
100 MHz
3
2/3
3
HM5264405FLTT-75*1
HM5264405FLTT-A60
HM5264405FLTT-B60*2
133 MHz
100 MHz
100 MHz
3
2/3
3
Note: 1. 100 MHz operation at CAS latency = 2.
2. 66 MHz operation at CAS latency = 2.
Package
400-mil 54-pin plastic TSOP II (TTP-54D)
2



Hitachi Semiconductor HM5264805F-B60
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
Pin Arrangement (HM5264165F)
VCC
DQ0
VCCQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VCCQ
DQ5
DQ6
VSSQ
DQ7
VCC
DQML
WE
CAS
RAS
CS
A13
A12
A10
A0
A1
A2
A3
VCC
54-pin TSOP
1 54
2 53
3 52
4 51
5 50
6 49
7 48
8 47
9 46
10 45
11 44
12 43
13 42
14 41
15 40
16 39
17 38
18 37
19 36
20 35
21 34
22 33
23 32
24 31
25 30
26 29
27 28
(Top view)
VSS
DQ15
VSSQ
DQ14
DQ13
VCCQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VCCQ
DQ8
VSS
NC
DQMU
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
Pin Description
Pin name
A0 to A13
DQ0 to DQ15
CS
RAS
CAS
Function
Pin name
Function
Address input
WE Write enable
Row address A0 to A11
DQMU/DQML Input/output mask
Column address A0 to A7
CLK
Clock input
Bank select address A12/A13 (BS) CKE
Clock enable
Data-input/output
Chip select
Row address strobe command
Column address strobe command
VCC
VSS
VCCQ
VSSQ
NC
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
3







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