CMOS PROM. HM6-6642B-9 Datasheet

HM6-6642B-9 PROM. Datasheet pdf. Equivalent

HM6-6642B-9 Datasheet
Recommendation HM6-6642B-9 Datasheet
Part HM6-6642B-9
Description 512 x 8 CMOS PROM
Feature HM6-6642B-9; HM-6642 March 1997 512 x 8 CMOS PROM Description The HM-6642 is a 512 x 8 CMOS NiCr fusible link Pr.
Manufacture Intersil Corporation
Datasheet
Download HM6-6642B-9 Datasheet




Intersil Corporation HM6-6642B-9
HM-6642
March 1997
512 x 8 CMOS PROM
Features
Description
• Low Power Standby and Operating Power
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100µA
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA at 1MHz
• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 120/200ns
• Industry Standard Pinout
• Single 5.0V Supply
• CMOS/TTL Compatible Inputs
• Field Programmable
• Synchronous Operation
• On-Chip Address Latches
• Separate Output Enable
The HM-6642 is a 512 x 8 CMOS NiCr fusible link
Programmable Read Only Memory in the popular 24 pin,
byte wide pinout. Synchronous circuit design techniques
combine with CMOS processing to give this device high
speed performance with very low power dissipation.
On-chip address latches are provided, allowing easy
interfacing with recent generation microprocessors that use
multiplexed address/data bus structures, such as the 8085.
The output enable controls, both active low and active high,
further simplify microprocessor system interfacing by
allowing output data bus control independent of the chip
enable control. The data output latches allow the use of the
HM-6642 in high speed pipelined architecture systems, and
also in synchronous logic replacement functions.
Applications for the HM-6642 CMOS PROM include low
power handheld microprocessor based instrumentation and
communications systems, remote data acquisition and
processing systems, processor control store, and synchro-
nous logic replacement.
All bits are manufactured storing a logical “0” and can be
selectively programmed for a logical “1” at any bit location.
Ordering Information
PACKAGE
SBDIP
SMD#
SLIM SBDIP
SMD#
CLCC
SMD#
TEMPERATURE RANGE
-40oC to +85oC
-55oC to +125oC
-40oC to +85oC
-55oC to +125oC
-40oC to +85oC
-55oC to +125oC
120ns
HM1-6642B-9
5962-8869002JA
HM6-6642B-9
5962-8869002LA
-
5962-88690023A
200ns
HM1-6642-9
5962-8869001JA
HM6-6642-9
5962-8869001LA
HM4-6642-9
5962-88690013A
PKG. NO.
D24.6
D24.6
D24.3
D24.3
J28.A
J28.A
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-1
File Number 3012.1



Intersil Corporation HM6-6642B-9
HM-6642
Pinouts
HM-6642 (SBDIP)
TOP VIEW
HM-6642 (CLCC)
TOP VIEW
A7 1
A6 2
A5 3
A4 4
A3 5
A2 6
A1 7
A0 8
Q0 9
Q1
10
Q2
11
GND
12
24 VCC
23 A8
22 G1
21 G2
20 G3
19 E
18 P
17 Q7
16 Q6
15 Q5
14 Q4
13 Q3
4 3 2 1 28 27 26
A4 5
25 G2
A3 6
24 G3
A2 7
23 E
A1 8
22 P
A0 9
21 NC
NC 10
20 Q7
Q0 11
19 Q6
12 13 14 15 16 17 18
PIN DESCRIPTION
PIN DESCRIPTION
NC No Connect
A0-A8
Address Inputs
E Chip Enable
Q Data Output
VCC
Power (+5V)
G1, G2, G3 Output Enable
P (Note) Program Enable
NOTE: P should be hardwired to GND
except during programming.
Functional Diagram
A8 A
A7
A6
LATCHED
6 GATED
ADDRESS
ROW
A5
A4
REGISTER
A
DECODER
64
A3 6
64 x 64
MATRIX
ALL LINES POSITIVE LOGIC - ACTIVE HIGH
THREE STATE BUFFERS:
A HIGH
OUTPUT ACTIVE
A
A2
A1
A0
LATCHED
ADDRESS
REGISTER
3
A
3
88 8888 8 8
GATED COLUMN
DECODER
D
DATA LATCHES:
L HIGH
Q=D
Q LATCHES ON RISING EDGE OF E
ADDRESS LATCHES AND GATED DECODERS:
LATCH ON FALLING EDGE OF E
GATE ON FALLING EDGE OF E
P SHOULD BE HARDWIRED TO GND EXCEPT
DURING PROGRAMMING
E 8-BIT DATA LATCH
G1
G2
G3
Q0 Q1 Q2 Q3
Q4 Q5 Q6 Q7
6-2



Intersil Corporation HM6-6642B-9
HM-6642
Programming
Introduction
The HM-6642 is a 512 word by 8-bit field Programmable
Read Only Memory utilizing nicrome fusible links as pro-
grammable memory elements. Selected memory locations
are permanently changed from their manufactured state, of
all low (VOL) to a logical high (VOH), by the controlled
application of programming potentials and pulses. Careful
adherence to the following programming specifications will
result in high programming yield. Both high VCC (6.0V) and
low VCC (4.0V) verify cycles are specified to assure the
integrity of the programmed fuse. This programming
specification, although complete, does not preclude rapid
programming. The worst case programming time required is
37.4 seconds, and typical programming time can be
approximately 4 seconds per device.
The chip (E) and output enable (G) are used during the
programming procedure. On PROMs which have more than
one output enable control G3 is to be used. The other output
enables must be held in the active, or enabled, state
throughout the entire programming sequence. The program-
mer designer is advised that all pins of the programmer’s
socket should be at ground potential when the PROM is
inserted into the socket. VCC must be applied to the PROM
before any input or output pin is allowed to rise (See Note).
Overall Programming Procedure
1. The address of the first bit to be programmed is
presented, and latched by the chip enable (E) falling
edge. The output is disabled by taking the output enable
G Low: The programming pin is enabled by taking (P)
high.
2. VCC is raised to the programming voltage level, 12.5V.
3. All data output pins are pulled up to VCC program. Then
the data output pin corresponding to the bit to be
programmed is pulled low for 100ms. Only one bit should
be programmed at a time.
4. The data output pin is returned to VCC, and the VCC pin
is returned to 6.0V.
5. The address of the bit is again presented, and latched by
a second chip enable falling edge.
6. The data outputs are enabled, and read, to verify that the
bit was successfully programmed.
a). If verified, the next bit to be programmed is addressed
and programmed.
b). If not verified, the programs verify sequence is
repeated up to 8 times total.
7. After all bits to be programmed have been verified at 6.0V,
the VCC is lowered to 4.0V and all bits are verified.
a). If all bits verify, the device is properly programmed.
b). If any bit fails to verify, the device is rejected.
Programming System Requirements
1. The power supply for the device to be programmed must
be able to be set to three voltages: 4.0V, 6.0V, 12.5V. This
supply must be able to supply 500mA average, and 1A
dynamic, currents to the PROM during programming. The
power supply rise fall times when switching between volt-
ages must be no quicker than 1ms.
2. The address drivers must be able to supply a VIH of 4.0V
and 6.0V and VIL when the system is at programming
voltages. (See Note)
3. The control input buffers must be able to maintain input
voltage levels of ≥ 70% and ≤ 20% VCC for VIH and VIL
levels, respectively. Notice that chip enable (E) and G
does not require a pull up to programming voltage levels.
The program control (P) must switch from ground to VIH
and from VIH to the VCC PGM level. (See Note)
4. The data input buffers must be able to sink up to 3mA
from the PROM’s output pins without rising more than
0.7V above ground, be able to hold the other outputs high
with a current source capability of 0.5mA to 2.0mA, and
not interfere with the reading and verifying of the data
output of the PROM. Notice that a bit to be programmed
is changed from a low state (VOL) to high (VOH) by pulling
low on the output pin. A suggested implementation is
open collector TTL buffers (or inverters) with 4.7kΩ pull
up resistors to VCC. (See Note)
NOTE: Never allow any input or output pin to rise more than 0.3V
above VCC, or fall more than 0.3V below ground.
6-3







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)