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HM6-6642B-9 Dataheets PDF



Part Number HM6-6642B-9
Manufacturers Intersil Corporation
Logo Intersil Corporation
Description 512 x 8 CMOS PROM
Datasheet HM6-6642B-9 DatasheetHM6-6642B-9 Datasheet (PDF)

HM-6642 March 1997 512 x 8 CMOS PROM Description The HM-6642 is a 512 x 8 CMOS NiCr fusible link Programmable Read Only Memory in the popular 24 pin, byte wide pinout. Synchronous circuit design techniques combine with CMOS processing to give this device high speed performance with very low power dissipation. On-chip address latches are provided, allowing easy interfacing with recent generation microprocessors that use multiplexed address/data bus structures, such as the 8085. The output enable.

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HM-6642 March 1997 512 x 8 CMOS PROM Description The HM-6642 is a 512 x 8 CMOS NiCr fusible link Programmable Read Only Memory in the popular 24 pin, byte wide pinout. Synchronous circuit design techniques combine with CMOS processing to give this device high speed performance with very low power dissipation. On-chip address latches are provided, allowing easy interfacing with recent generation microprocessors that use multiplexed address/data bus structures, such as the 8085. The output enable controls, both active low and active high, further simplify microprocessor system interfacing by allowing output data bus control independent of the chip enable control. The data output latches allow the use of the HM-6642 in high speed pipelined architecture systems, and also in synchronous logic replacement functions. Applications for the HM-6642 CMOS PROM include low power handheld microprocessor based instrumentation and communications systems, remote data acquisition and processing systems, processor control store, and synchronous logic replacement. All bits are manufactured storing a logical “0” and can be selectively programmed for a logical “1” at any bit location. Features • Low Power Standby and Operating Power - ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100µA - ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA at 1MHz • Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 120/200ns • Industry Standard Pinout • Single 5.0V Supply • CMOS/TTL Compatible Inputs • Field Programmable • Synchronous Operation • On-Chip Address Latches • Separate Output Enable Ordering Information PACKAGE SBDIP SMD# SLIM SBDIP SMD# CLCC SMD# TEMPERATURE RANGE -40oC to +85oC -55oC to +125oC -40oC to +85oC -55oC to +125oC -40oC to +85oC -55oC to +125oC 120ns HM1-6642B-9 5962-8869002JA HM6-6642B-9 5962-8869002LA 5962-88690023A 200ns HM1-6642-9 5962-8869001JA HM6-6642-9 5962-8869001LA HM4-6642-9 5962-88690013A PKG. NO. D24.6 D24.6 D24.3 D24.3 J28.A J28.A CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 File Number 3012.1 6-1 HM-6642 Pinouts HM-6642 (SBDIP) TOP VIEW A6 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 VCC 23 A8 22 G1 21 G2 20 G3 19 E 18 P 17 Q7 16 Q6 NC 15 Q5 14 Q4 13 Q3 Q0 11 12 Q1 13 Q2 14 GND 15 NC 16 Q3 17 Q4 18 10 20 19 Q7 Q6 A2 A1 A0 7 8 9 23 22 21 E P NC A4 A3 5 6 A5 HM-6642 (CLCC) TOP VIEW VCC NC G1 A7 A8 PIN DESCRIPTION PIN NC 25 24 G2 G3 DESCRIPTION No Connect Address Inputs Chip Enable Data Output Power (+5V) Output Enable Program Enable 4 3 2 1 28 27 26 A0-A8 E Q VCC G1, G2, G3 P (Note) NOTE: P should be hardwired to GND except during programming. Functional Diagram A8 A7 A6 A5 A4 A3 LATCHED ADDRESS REGISTER 6 A 6 GATED ROW DECODER 64 64 x 64 MATRIX ALL LINES POSITIVE LOGIC - ACTIVE HIGH THREE STATE BUFFERS: OUTPUT ACTIVE A HIGH 8 A A2 A1 A0 LATCHED ADDRESS REGISTER 3 A 3 D E 8-BIT DATA LATCH GATED COLUMN DECODER 8 8 8 8 8 8 8 DATA LATCHES: Q=D L HIGH Q LATCHES ON RISING EDGE OF E ADDRESS LATCHES AND GATED DECODERS: LATCH ON FALLING EDGE OF E GATE ON FALLING EDGE OF E P SHOULD BE HARDWIRED TO GND EXCEPT DURING PROGRAMMING A G1 G2 G3 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 6-2 Q5 HM-6642 Programming Introduction The HM-6642 is a 512 word by 8-bit field Programmable Read Only Memory utilizing nicrome fusible links as programmable memory elements. Selected memory locations are permanently changed from their manufactured state, of all low (VOL) to a logical high (VOH), by the controlled application of programming potentials and pulses. Careful adherence to the following programming specifications will result in high programming yield. Both high VCC (6.0V) and low VCC (4.0V) verify cycles are specified to assure the integrity of the programmed fuse. This programming specification, although complete, does not preclude rapid programming. The worst case programming time required is 37.4 seconds, and typical programming time can be approximately 4 seconds per device. The chip (E) and output enable (G) are used during the programming procedure. On PROMs which have more than one output enable control G3 is to be used. The other output enables must be held in the active, or enabled, state throughout the entire programming sequence. The programmer designer is advised that all pins of the programmer’s socket should be at ground potential when the PROM is inserted into the socket. VCC must be applied to the PROM before any input or output pin is allowed to rise (See Note). Overall Programming Procedure 1. The address of the first bit to be programmed is presented, and latched by the chip enable (E) falling edge. The output is disabled by taking the output enable G Low: The programming pin is enabled by taking (P) high. 2. VCC is raised to the programming voltage level, 12.5V. 3. All data output pins are pulled up to VCC pr.


HM6-6642-9 HM6-6642B-9 HM6116


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