x 4-bit. HM624100H Datasheet

HM624100H 4-bit. Datasheet pdf. Equivalent

HM624100H Datasheet
Recommendation HM624100H Datasheet
Part HM624100H
Description 4M High Speed SRAM (1-Mword x 4-bit)
Feature HM624100H; HM624100H Series 4M High Speed SRAM (1-Mword × 4-bit) ADE-203-789D (Z) Rev. 1.0 Sep. 15, 1998 Descr.
Manufacture Hitachi Semiconductor
Datasheet
Download HM624100H Datasheet




Hitachi Semiconductor HM624100H
HM624100H Series
4M High Speed SRAM (1-Mword × 4-bit)
ADE-203-789D (Z)
Rev. 1.0
Sep. 15, 1998
Description
The HM624100H is a 4-Mbit high speed static RAM organized 1-Mword × 4-bit. It has realized high speed
access time by employing CMOS process (4-transistor + 2-poly resistor memory cell) and high speed circuit
designing technology. It is most appropriate for the application which requires high speed and high density
memory, such as cache and buffer memory in system. The HM624100H is packaged in 400-mil 32-pin SOJ
for high density surface mounting.
Features
Single 5.0 V supply : 5.0 V ± 10 %
Access time 10/12/15 ns (max)
Completely static memory
No clock or timing strobe required
Equal access and cycle times
Directly TTL compatible
All inputs and outputs
Operating current : 200/180/160 mA (max)
TTL standby current : 70/60/50 mA (max)
CMOS standby ccurrent : 5 mA (max)
: 1.2 mA (max) (L-version)
Data retension current : 0.8 mA (max) (L-version)
Data retension voltage : 2.0 V (min) (L-version)
Center VCC and VSS type pinout



Hitachi Semiconductor HM624100H
HM624100H Series
Ordering Information
Type No.
HM624100HJP-10
HM624100HJP-12
HM624100HJP-15
HM624100HLJP-10
HM624100HLJP-12
HM624100HLJP-15
Access time
10 ns
12 ns
15 ns
10 ns
12 ns
15 ns
Package
400-mil 32-pin plastic SOJ (CP-32DB)
Pin Arrangement
HM624100HJP/HLJP Series
A0 1
A1 2
A2 3
A3 4
A4 5
CS 6
I/O1 7
VCC
VSS
I/O2
8
9
10
WE 11
A5 12
A6 13
A7 14
A8 15
A9 16
32 A19
31 A18
30 A17
29 A16
28 A15
27 OE
26 I/O4
25 VSS
24 VCC
23 I/O3
22 A14
21 A13
20 A12
19 A11
18 A10
17 NC
(Top view)
2



Hitachi Semiconductor HM624100H
Pin Description
Pin name
A0 to A19
I/O1 to I/O4
CS
OE
WE
VCC
VSS
NC
Function
Address input
Data input/output
Chip select
Output enable
Write enable
Power supply
Ground
No connection
HM624100H Series
Block Diagram
(LSB)
A1
A17
A7
A11
A16
A2
A6
A5
(MSB)
I/O1
.
.
.
I/O4
WE
CS
Row
decoder
Memory matrix
256 rows × 16 columns ×
256 blocks × 4 bit
(4,194,304 bits)
Internal
voltage
generater
VCC
VSS
CS
Input
data
control
Column I/O
Column decoder
CS
A10 A8 A9 A19 A12 A13 A14 A0 A18 A15 A3 A4
(LSB)
(MSB)
OE
CS
3







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