x 8-bit. HM6264B Datasheet

HM6264B 8-bit. Datasheet pdf. Equivalent

HM6264B Datasheet
Recommendation HM6264B Datasheet
Part HM6264B
Description 64 k SRAM (8-kword x 8-bit)
Feature HM6264B; HM6264B Series 64 k SRAM (8-kword × 8-bit) ADE-203-454B (Z) Rev. 2.0 Nov. 1997 Description The Hita.
Manufacture Hitachi Semiconductor
Datasheet
Download HM6264B Datasheet




Hitachi Semiconductor HM6264B
HM6264B Series
64 k SRAM (8-kword × 8-bit)
ADE-203-454B (Z)
Rev. 2.0
Nov. 1997
Description
The Hitachi HM6264B is 64k-bit static RAM organized 8-kword × 8-bit. It realizes higher performance
and low power consumption by 1.5 µm CMOS process technology. The device, packaged in 450 mil
SOP (foot print pitch width), 600 mil plastic DIP, 300 mil plastic DIP, is available for high density
mounting.
Features
High speed
Fast access time: 85/100 ns (max)
Low power
Standby: 10 µW (typ)
Operation: 15 mW (typ) (f = 1 MHz)
Single 5 V supply
Completely static memory
No clock or timing strobe required
Equal access and cycle times
Common data input and output
Three state output
Directly TTL compatible
All inputs and outputs
Battery backup operation capability



Hitachi Semiconductor HM6264B
HM6264B Series
Ordering Information
Type No.
HM6264BLP-8L
HM6264BLP-10L
HM6264BLSP-8L
HM6264BLSP-10L
HM6264BLFP-8LT
HM6264BLFP-10LT
Access time
85 ns
100 ns
85 ns
100 ns
85 ns
100 ns
Pin Arrangement
Package
600-mil, 28-pin plastic DIP (DP-28)
300-mil, 28-pin plastic DIP(DP-28N)
450-mil, 28-pin plastic SOP(FP-28DA)
Pin Description
Pin name
A0 to A12
I/O1 to I/O8
CS1
CS2
HM6264BLP/BLSP/BLFP Series
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VCC
27 WE
26 CS2
25 A8
24 A9
23 A11
22 OE
21 A10
20 CS1
19 I/O8
18 I/O7
17 I/O6
16 I/O5
15 I/O4
(Top view)
Function
Address input
Data input/output
Chip select 1
Chip select 2
Pin name
WE
OE
NC
VCC
VSS
Function
Write enable
Output enable
No connection
Power supply
Ground



Hitachi Semiconductor HM6264B
Block Diagram
A11
A8
A9
A7
A12
A5
A6
A4
I/O1
I/O8
CS2
CS1
WE
OE
HM6264B Series
Row
decoder
Memory array
256 × 256
VCC
VSS
Input
data
control
Column I/O
Column decoder
A1 A2 A0 A10 A3
Timing pulse generator
Read, Write control







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